MAX8661ETL+ Maxim Integrated Products, MAX8661ETL+ Datasheet - Page 29

• Manufacturer Part Number: MAX8661ETL+
• Description: IC POWER MANAGE XSCALE 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8661ETL+

• Applications: Processor
• Voltage - Supply: 2.6 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

between R
56kΩ R
Marvell PXA3xx processors; 200µs after being enabled,
REG3 and REG4 linearly ramp from 0V to the set output
voltage at the rate set by R
REG4 are disabled, the output voltage decays at a rate
determined by the output capacitance, internal 550Ω
discharge resistance, and the external load.
Active ramp-down functionality is inherent in forced-
PWM operation. In normal-mode operation, active ramp
down is enabled by setting ARD3 and ARD4 (Table 9).
With “active ramp-down” enabled, the regulator output
voltage ramps down at the rate set by R
loads, the regulator must sink current from the output
capacitor to actively ramp down the output voltage. In
normal mode, with “active ramp-down” disabled, the
regulator output voltage ramps down at the rate deter-
mined by the output capacitance and the external load;
small loads result in an output-voltage decay that is slow-
er than that specified by R
RAMPRATE) result in an output-voltage decay that is no
faster than that specified by R
80µs after being enabled, REG5 linearly ramps from 0V
to the set output voltage in 225µs. The ramp rate during
a positive voltage change (i.e., 1.8V to 1.9V) is set with
R
1.8V), the REG5 output voltage decays at a rate deter-
mined by the output capacitance and the external load;
however, ramp-down is no faster than the rate specified
by R
decays at a rate determined by the output capacitance,
internal 2kΩ discharge resistance, and the external load.
60µs after being enabled by I
early ramp from 0V to the set output voltage in 450µs.
REG6 and REG7 do not have positive voltage-change
Table 5. Enable Signals
RAMP
RAMP
V7 (VCC_CARD2) (MAX8660/MAX8660A only)
. During a negative voltage change (i.e., 1.9V to
V1 (VCC_IO) (MAX8660/MAX8660A only)
RAMP
. When REG5 is disabled, the output voltage
RAMP
Voltage Management for Mobile Applications
High-Efficiency, Low-I
satisfies the typical requirements of
and the output-voltage ramp rates. A
POWER DOMAIN
V6 (VCC_CARD1)
V8 (VCC_BBATT)
______________________________________________________________________________________
V4 (VCC_SRAM)
V3 (VCC_APPS)
V2 (VCC_MEM)
V5 (VCC_MVT)
RAMP
RAMP
RAMP
2
C, REG6 and REG7 lin-
, large loads (> C
.
. When REG3 and
RAMP
. With small
OUT
HARDWARE
x
MAXIM ENABLE SIGNAL
EN34
EN1
EN2
EN5
—
—
(i.e., 1.8V to 2.5V) ramp-rate control. During a positive
voltage change, the output-voltage dV/dt is as fast as
possible. To avoid this fast output dV/dt, disable REG6
or REG7 before changing the output. With this method,
the soft-start ramp rate limits the output dV/dt, and
therefore, the input current is controlled. During a nega-
tive voltage change (i.e., 2.5V to 1.8V), the REG6 or
REG7 output voltage decays at a rate determined by
the output capacitance and the external load. When
REG6 or REG7 is disabled, the output voltage decays
at a rate determined by the output capacitance, internal
350Ω discharge resistance, and the external load.
As shown in Table 5, the MAX8660/MAX8661 feature
numerous enable signals for flexibility in many applica-
tions. In a typical application with the Marvell PXA3xx
processor, many of these enable signals are connected
together. EN1, EN2, and EN5 typically connect to the
SYS_EN output. With this connection, REG5 is the first
supply to rise (if IN5 is connected to IN). EN34 typically
connects to Marvell’s PWR_EN output. Alternatively,
REG3 and REG4 can be activated by the I
(see the REG3/REG4 Enable (EN34, EN3, EN4) section
for more information). REG6 and REG7 are activated by
the serial interface. REG8 has no enable input and
always remains on as long the MAX8660/MAX8661 are
powered between the UVLO and OVLO range. All regu-
lators are forced off during UVLO and OVLO. See the
Undervoltage and Overvoltage Lockout section for
more information.
Note: The logic that controls the Marvell PXA3xx
processor SYS_EN and PWR_EN signals is powered
from the VCC_BBATT power domain.
Q
Always on
, PMICs with Dynamic
Enable Signals (EN_, PWR_EN, SYS_EN, I
EN3 (OVER1)
EN4 (OVER1)
EN6 (OVER2)
EN7 (OVER2)
SOFTWARE
—
—
—
APPLICATIONS PROCESSOR
Power Sequencing
ENABLE SIGNAL
Standard I
PWR_EN &
PWR_I
SYS_EN
—
2
C
2
2
C interface
C
2
29
C)