IR3504MPBF International Rectifier, IR3504MPBF Datasheet - Page 14

• Manufacturer Part Number: IR3504MPBF
• Description: IC CTRL XPHASE AMD SVID 32-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase3™r

Specifications of IR3504MPBF

• Applications: Processor
• Current - Supply: 10mA
• Voltage - Supply: 4.75 V ~ 7.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: *
• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IR3504
IR3504 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3504 is shown in Figure 8. The following discussions are applicable to either output
plane unless otherwise specified.
Serial VID Control
The two Serial VID Interface (SVID) pins SVC and SVD are used to program the Boot VID voltage upon assertion of
ENABLE while PWROK is de-asserted. See Table 1 for the 2-bit Boot VID codes. Both VDAC1 and VDAC2
voltages will be programmed to the Boot VID code until PWROK is asserted. The Boot VID code is stored by the
IR3504 to be utilized again if PWROK is de-asserted.
Serial VID communication from the processor is enabled after the PWROK is asserted. Addresses and data are
serially transmitted in 8-bit words. The IR3504 has three fixed addresses to control VDAC1, VDAC2, or both
VDAC1 and VDAC2 (See Table 6 for addresses). The first data bit of the SVID data word represents the PSI_L bit
and will be ignored by the IR3504 therefore this system will never enter a power-saving mode. The remaining data
bits SVID[6:0] select the desired VDACx regulation voltage as defined in Table 3. SVID[6:0] are the inputs to the
Digital-to-Analog Converter (DAC) which then provides an analog reference voltage to the transconductance type
buffer amplifier. This VDACx buffer provides a system reference on the VDACx pin. The VDACx voltage along with
error amplifier and remote sense differential amplifier input offsets are post-package trimmed to provide a 0.5%
system set-point accuracy, as measured in Figures 3A and 3B. VDACx slew rates are programmable by properly
selecting external series RC compensation networks located between the VDACx and the LGND pins. The VDACx
source and sink currents are derived off the external oscillator frequency setting resistor, R
. The programmable
ROSC
slew rate enables the IR3504 to smoothly transition the regulated output voltage throughout VID transitions. This
results in power supply input and output capacitor inrush currents along with output voltage overshoot to be well
controlled.
The two Serial VID Interface (SVID) pins SVC and SVD can also program the VFIX VID voltage upon assertion of
ENABLE while PWROK is equal to VCCL. See Table 2 for the 2-bit VFIX VID codes. Both VDAC1 and VDAC2
voltages will be programmed to the VFIX code.
The SVC and SVD pins require external pull-up biasing and should not be floated.
Output 1 (VDD) Adaptive Voltage Positioning
The IR3504 provides Adaptive Voltage Positioning (AVP) on the output1 plane only. AVP helps reduces the peak
to peak output voltage excursions during load transients and reduces load power dissipation at heavy load. The
circuitry related to the voltage positioning is shown in Figure 9. Resistor R
is connected between the error
FB1
amplifiers inverting input pin FB1 and the remote sense differential amplifier output, VOUT1. An internal current sink
on the FB1 pin along with R
provides programmability of a fixed offset voltage above the VDAC1 voltage. The
FB1
offset voltage generated across R
forces the converter’s output voltage higher to maintain a balance at the error
FB1
amplifiers inputs. The FB1 sink current is derived by the external resistor R
that programs the oscillator
ROSC
frequency.
The VDRP1 pin voltage is a buffered reproduction of the IIN1 pin which is connected to the current share bus
ISHARE. The voltage on ISHARE represents the system average inductor current information. At each phase IC,
an RC network across the inductor provides current information which is gained up 32.5X and then added to the
VDAC
voltage. This phase current information is provided on the ISHARE bus via a 3K resistor in the phase ICs.
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July 28, 2009