IR3504MTRPBF International Rectifier, IR3504MTRPBF Datasheet - Page 20

• Manufacturer Part Number: IR3504MTRPBF
• Description: IC CTRL XPHASE3 SVID 32-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase3™r

Specifications of IR3504MTRPBF

• Applications: Processor
• Current - Supply: 10mA
• Voltage - Supply: 4.75 V ~ 7.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: *
• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial VID Interface Protocol and VID-on-the-fly Transition
The IR3504 supports the AMD SVI bus protocol and the AMD Server and desktop SVI wire protocol which is based
on fast-mode I
SVD. The SVC pin of the IR3504 does not have an open drain output since AMD SVID protocol does not support
slave clock stretching.
The IR3504 transitions from a 2-bit Boot VID mode to SVI mode upon assertion of PWROK. The SMBus send byte
protocol is used by the IR3504 VID-on-the-fly transactions. The IR3504 will wait until it detects a start bit which is
defined as an SVD falling edge while SVC is high. A 7bit address code plus one write bit (low) should then follow
the start bit. This address code will be compared against an internal address table and the IR3504 will reply with an
acknowledge ACK bit if the address is one of the three stored addresses otherwise the ACK bit will not be sent out.
The SVD pin is pulled low by the IR3504 to generate the ACK bit. Table 4 has the list of addresses recognized by
the IR3504.
The processor should then transmit the 8-bit data word immediately following the ACK bit. Data bit 7 is the PSI_L
bit which is followed by the 7Bit AMD code. The IR3504 replies again with an ACK bit once the data is received. If
the received data is not a VID-OFF command, the IR3504 immediately changes the DAC analog outputs to the new
target. VDAC1 and VDAC2 then slew to the new VID voltages. See Figure 12 for a send byte example.
Table 4 - SVI Send Byte Address Table
Note: ‘x’ in the above Table 4 means the bit could be either ‘1’ or ‘0’.
SVI Address [6:0] + Wr
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110xx100b
110xx010b
110xx110b
2
C. SVID commands from an AMD processor are communicated through SVID bus pins SVC and
Set VID on both Output 1 and Output 2
Set VID only on Output 1
Set VID only on Output 2
Figure 12 Send Byte Example
Description
July 28, 2009
IR3504