IR3521MTRPBF International Rectifier, IR3521MTRPBF Datasheet - Page 28

• Manufacturer Part Number: IR3521MTRPBF
• Description: IC CTRL XPHASE3 SVID 32-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase3™r

Specifications of IR3521MTRPBF

• Applications: Processor
• Current - Supply: 10mA
• Voltage - Supply: 4.75 V ~ 7.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: *
• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DESIGN PROCEDURES - IR3521 AND IR3508 CHIPSET
IR3521 EXTERNAL COMPONENTS
All the output components are selected using one output but suitable for both unless otherwise specified.
Oscillator Resistor R
The IR3521 generates square wave pulses to synchronize the phase ICs. The switching frequency of the each
phase converter equals the PHSOUT frequency, which is set by the external resistor R
determine the R
number.
Soft Start Capacitor C
The Soft Start capacitor C
PGOOD delay time and over-current fault latch delay time after PGOOD.
SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 11. Once the ENABLE
pin rises above 1.65V, there is a soft-start delay time TD1 during which SS/DEL pin is charged from zero to 1.4V.
Once SS/DEL reaches 1.4V the error amplifier output is released to allow the soft start. The soft start time, TD2,
represents the time during which converter voltage rises from zero to pre-PWROK VID voltage and the SS/DEL pin
voltage rises from 1.4V to pre-PWROK VID voltage plus 1.4V. PGOOD delay time TD3 is the time period from VR
reaching the pre-PWROK VID voltage to the PGOOD signal assertion.
Calculate C
The soft start delay time TD1 and PGOOD delay time TD3 are determined by equation (2) and (3) respectively.
Once C
VDAC Slew Rate Programming Capacitor C
The slew rate of VDAC down-slope SR
where I
determined by (6). The up and down slow are equal due to symmetrical sink and source capabilities of the VDAC
buffer.
SS/DEL
SINK
SS/DEL
is the VDAC buffer sink current. The resistor R
is chosen, use equation (4) to calculate the maximum over-current fault latch delay time
TD
C
TD
ROSC
based on the required soft start time TD2.
SS
1
3
/
DEL


R
SS/DEL
osc
value). The CLKOUT frequency equals the switching frequency multiplied by the phase
C
C
t
OCDEL

SS
SS
SS/DEL
/
TD
/
DEL
V
I
DEL
CHG
pre
2

( *

1 *
*
PWROK
C
. 3
I
programs four different time parameters: soft start delay time, soft start time,
4 .
SS
92
CHG
I
/
I

DEL
DISCHG
DOWN

CHG
C

V
*
50
pre
SS
TD
. 0

/
can be programmed by the external capacitor C
DEL
PWROK
V
*
VDAC
12
2
10
pre
*
1 *


50

PWROK
6

and Resistor R
C
4 .
Page 28
*
. 1
SS
10
47
) 4
/
DEL

*

6
10
C
*
SS
. 0

6
/
12
VDAC
DEL
VDAC
( *
is used to compensate VDAC circuit and is
. 3
92
50
*

10
V
pre

6
(2)

PWROK
(1)

. 1
) 4
ROSC
VDAC
(4)
IR3521
(use Figure 2 to
as defined in (5),
V3.03
t
OCDEL.
(3)