MC10XS3435DPNA Freescale Semiconductor, MC10XS3435DPNA Datasheet - Page 46

• Manufacturer Part Number: MC10XS3435DPNA
• Description: IC SWITCH HIGH SIDE QUAD 24QFN
• Manufacturer: Freescale Semiconductor
• Type: High Side Switchr

Specifications of MC10XS3435DPNA

• Number Of Outputs: 4
• Rds (on): 2 x 10 mOhm, 2 x 35 mOhm
• Internal Switch(s): Yes
• Current Limit: 5A
• Voltage - Input: 4 ~ 28 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-PQFN, 24-PowerQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
Introduction
technical data sheet. The addendum provides thermal performance
information that may be critical in the design and development of system
applications. All electrical, application and packaging information is
provided in the data sheet.
Package and Thermal Considerations
package independently heating with P
temperatures, T
reference temperature while only heat source 1 is heating with P
reference temperature while heat source 2 is heating with P
to R
one package to another in a standardized environment. This methodology is not meant to and will not predict the performance
of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to
the standards listed below.
Standards
Table 25. Thermal Performance Comparison
46
10XS3435
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
Notes:
This thermal addendum is provided as a supplement to the 10XS3435
This 10XS3435 is a dual die package. There are two heat sources in the
For m, n = 1, R
For m = 1, n = 2, R
The stated values are solely for a thermal performance comparison of
Resistance
1.
2.
3.
4.
5.
R
R
R
R
θJ21
Thermal
θ
θ
θ
θJCmn
JA mn
JB mn
JA mn
Per JEDEC JESD51-2 at natural convection, still air
condition.
2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
and R
(5)
(1)(2)
(2)(3)
(1)(4)
θJ22
T
T
J1
J1
J2
θJA11
and T
, respectively.
m = 1,
1 = Power Chip, 2 = Logic Chip
27.13
14.31
47.77
n = 1
1.38
=
θJA12
is the thermal resistance from Junction 1 to the
J2
R
R
, and a thermal resistance matrix with R
θJA11
θJA21
is the thermal resistance from Junction 1 to the
m = 1, n = 2
m = 2, n = 1
R
R
θJA12
θJA22
18.31
36.90
6.54
0.00
1
and P
.
2
P
P
. This results in two junction
1
2
[°C/W]
m = 2,
35.53
23.61
54.35
n = 2
0.91
2
. This applies
1
.
θJAmn
Figure 16. Detail of Copper Traces Under Device with
.
Note For package dimensions, refer to
the 10XS3435 data sheet.
10XS3435PNA
Analog Integrated Circuit Device Data
24-PIN PQFN (12 x 12)
Thermal Vias
98ARL10596D
PNA SUFFIX
24-PIN
PQFN
Freescale Semiconductor
0.2mm
0.5mm dia.
0.2mm