LTC1473IGN Linear Technology, LTC1473IGN Datasheet - Page 8

• Manufacturer Part Number: LTC1473IGN
• Description: IC SWITCH DVR PWRPATH DUAL16SSOP
• Manufacturer: Linear Technology
• Series: PowerPath™r

Specifications of LTC1473IGN

• Applications: Handheld/Mobile Devices
• Fet Type: N-Channel
• Number Of Outputs: 2
• Internal Switch(s): No
• Delay Time - On: 22µs
• Delay Time - Off: 1µs
• Voltage - Supply: 4.75 V ~ 30 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
LTC1473
After the transition period, the V
selected switch pair rises to approximately 5.6V. The gate
drive is set at 5.6V to provide ample overdrive for standard
logic-level MOSFET switches without exceeding their
maximum V
In the event of a fault condition the current limit loop will
limit the inrush current into the short. At the instant the
MOSFET switch is in current limit, i.e., when the voltage
drop across R
timing. It will continue to time as long as the MOSFET
switch is in current limit. Eventually the preset time will
lapse and the MOSFET switch will latch off. The latch is
reset by deselecting the gate drive input. Fault time-out is
programmed by an external capacitor connected between
the TIMER pin and ground.
POWER PATH SWITCHING CONCEPTS
Power Source Selection
The LTC1473 drives low-loss switches to direct power in
the main power path of a single or dual rechargeable
battery system, the type found in many notebook comput-
ers and other portable equipment.
Figure 3 is a conceptual block diagram that illustrates the
main features of an LTC1473 dual battery power manage-
ment system starting with the three main power sources
and ending at the output load (i.e.: system DC/DC
regulator).
8
GS
SENSE
rating.
U
is 200mV, a fault timer will start
INFORMATION
BAT1
BAT2
DCIN
U
GS
SW A1/B1
of both MOSFETs in the
W
LTC1473
Figure 3. LTC1473 PowerPath Conceptual Diagram
SW A2/B2
U
CURRENT
LIMITING
INRUSH
Switches SW A1/B1 and SW A2/B2 direct power from
either batteries to the input of the DC/DC switching regu-
lator. Each of the switches is controlled by a TTL/CMOS
compatible input that can interface directly with a power
management system P.
Using Tantalum Capacitors
The inrush (and “outrush”) current of the system DC/DC
regulator input capacitor is limited by the LTC1473, i.e.,
the current flowing both in and out of the capacitor during
transitions from one input power source to another is
limited. In many applications, this inrush current limiting
makes it feasible to use smaller tantalum surface mount
capacitors in place of larger aluminum electrolytics.
Note: The capacitor manufacturer should be consulted for
specific inrush current specifications and limitations and
some experimentation may be required to ensure compli-
ance with these limitations under all possible operating
conditions.
Back-to-Back Switch Topology
The simple SPST switches shown in Figure 3 actually
consist of two back-to-back N-channel switches. These
low-loss N-channel switch pairs are housed in 8-pin SO
and SSOP packaging and are available from a number of
manufacturers. The back-to-back topology eliminates the
problems associated with the inherent body diodes in
power MOSFET switches and allows each switch pair to
MANAGEMENT
POWER
P
+
C
IN
1473 F03
REGULATOR
SWITCHING
EFFICIENCY
DC/DC
OUTPUT LOAD
HIGH
12V
5V
3.3V