A4931MET-T Allegro Microsystems Inc, A4931MET-T Datasheet - Page 8

• Manufacturer Part Number: A4931MET-T
• Description: IC DC MOTOR PREDRIVER 3PH 28QFN
• Manufacturer: Allegro Microsystems Inc

Specifications of A4931MET-T

• Applications: DC Motor Driver, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Voltage - Supply: 8 V ~ 33 V
• Operating Temperature: -20°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Load: -

by holding ENB high for longer than 3 ms. Note that Brake mode
overrides Standby mode, so hold the BRAKEZ pin high in order
to enter Standby mode.
Charge Pump
supply above V
age on the VCP pin is internally monitored, and in case of a fault
condition, the outputs of the device are disabled.
Fault Shutdown
junction temperature or due to low voltage on VCP or VBB,
the outputs of the device are disabled until the fault condition is
removed. At power-up the UVLO circuit disables the drivers.
Overvoltage Protection
a hazardous voltage is present due to the motor generator pump-
ing up the supply bus. When the voltage exceeds V
synchronous rectification feature is disabled.
Overtemperature Protection
approximately 170°C, the Thermal Shutdown function will dis-
able the outputs until the internal temperature falls below the
15°C hysteresis.
Hall State Reporting
that changes state at each transition of an external Hall element.
The FG2 pin is an open drain output that changes state at each
HAx transition.
A4931
BB
The internal charge pump is used to generate a
to drive the high-side MOSFETs. The volt-
In the event of a fault due to excessive
The FG1 pin is an open drain output
VBB is monitored to determine if
If die temperature exceeds
BBOV
3-Phase Brushless DC Motor Pre-Driver
, the
Lock Detect Function
condition under either of these two different conditions:
• The FG1 signal is not consistently changing.
• The proper commutation sequence is not being followed. The
motor can be locked in a condition in which it toggles between
two specific Hall device states.
Both of these fault conditions are allowed to persist for period
of time, t
produces a triangle waveform (1.67 V peak-to-peak) with fre-
quency linearly related to the capacitor value. t
127 cycles of this triangle waveform, or:
After the wait time, t
and the fault is latched. These fault conditions can only be cleared
by any one of the following actions:
• Rising or falling edge on the DIR pin
• VBB UVLO threshold exceeded (during power-up cycle)
• ENB pin held high for > t
The Lock Detect function can be disabled by connecting CLD to
GND.
When the A4931 is in Brake mode, the Lock Detect counter is
disabled.
lock
. t
lock
is set by capacitor connected to CLD pin. C
lock
t
lock
, has expired, the outputs are disabled,
= C
lock
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
The IC will evaluate a locked rotor
LD
/ 2
× 20 s/μF
lock
is defined as
LD
8