A3932SEQ Allegro Microsystems Inc, A3932SEQ Datasheet - Page 7

• Manufacturer Part Number: A3932SEQ
• Description: IC CTRLR MOSFET 3PH 32-PLCC
• Manufacturer: Allegro Microsystems Inc

Specifications of A3932SEQ

• Applications: DC Motor Controller, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Voltage - Supply: 18 V ~ 50 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output: -
• Voltage - Load: -

A3932
23,37,38
4,5,18,
LD
10
11
12
13
14
15
16
17
19
20
21
22
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
6
7
8
9
RESET
BRAKE
SENSE
FAULT
MODE
VREG
AGND
PGND
Name
DEAD
LCAP
TACH
PWM
GHC
GHB
GHA
GLC
GLB
GLA
VBB
REF
DIR
SC
NC
CC
SB
CB
CA
SR
RC
SA
H1
H3
H2
Terminal Descriptions
Three-Phase Power MOSFET Controller
RESET — A logic input used to enable the device, internally
pulled up to V
and force all gate drivers to 0 V, coasting the motor. A RESET
= 0 allows the gate drive to follow the commutation logic. The
RESET = 1 overrides BRAKE.
GLA/GLB/GLC — Low-side, gate-drive outputs for ex ter nal
NMOS drivers. External series-gate resistors (as close as pos-
sible to the NMOS gate) can be used to con trol the slew rate
seen at the power-driver gate, thereby controlling the di/dt and
dv/dt of the SA/SB/SC outputs. GLx = 1 (or “high”) means that
the upper half (PMOS) of the driver is turned on and its drain
will source current to the gate of the low-side FET in the exter-
nal motor-driving bridge. GLx = 0 (or “low”) means that the
lower half (NMOS) of the driver is turned on and its drain will
sink current from the external FET’s gate circuit.
SA/SB/SC — Directly connected to the motor, these terminals
sense the volt ag es switched across the load. These ter mi nals are
also connected to the neg a tive side of the bootstrap ca pac i tors
and are the negative supply connections for the fl oating high-
side drivers.
GHA/GHB/GHC — High-side, gate-drive outputs for external
NMOS drivers. External se ries-gate resistors can be used to
control the slew rate seen at the power-driver gate, thereby con-
trolling the di/dt and dv/dt of the SA/SB/SC outputs.
GHx = 1 (or “high”) means that the upper half (PMOS) of the
driver is turned on and its drain will source current to the gate of
the high-side FET in the external motor-driving bridge. GHx =
0 (or “low”) means that the lower half (NMOS) of the driver is
turned on and its drain will sink current from the external FET’s
gate circuit.
CA/CB/CC — High-side connections for the bootstrap ca pac i-
tors, positive supply for high-side gate drivers. The boot strap
capacitors are charged to approximately V
ci at ed output Sx terminal is low. When the output swings high,
the voltage on this ter mi nal rises with the output to provide the
boosted gate voltage needed for N-channel power MOSFETs.
LCAP
(+5 V). A RESET = 1 will disable the de vice
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
REG
when the as so -
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