ATA6833-PLQW Atmel, ATA6833-PLQW Datasheet - Page 10

• Manufacturer Part Number: ATA6833-PLQW
• Description: IC BLDC MOTOR DVR/LIN SBC 48VQFN
• Manufacturer: Atmel
• Type: 3 Phase Brushless DC Motor Controllerr

Specifications of ATA6833-PLQW

• Applications: DC Motor Controller, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Voltage - Supply: 5.5 V ~ 22.3 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Product: Fan / Motor Controllers / Drivers
• Supply Current: 7 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.6
3.7
10
Output Drivers and Control Inputs IL1-IL3, IH1-IH3
VG Regulator
Atmel ATA6833/ATA6834 [Preliminary]
The VG regulator provides a stable voltage to supply the low-side gate drivers and to deliver
sufficient voltage for the external low-side Power-NMOS transistors. Typically the output volt-
age is 12V. In order to guarantee reliable operation even with a low battery voltage, the VG
regulator is supplied by the charge pump output. For stability, an external ceramic capacitor of
typically 470nF has to be provided. There is no internal supervision of the VG output voltage.
This IC offers six push-pull output drivers for the external low-side and high-side power-NMOS
transistors. To guarantee reliable operation, the low-side drivers are supplied by the VG regu-
lator while the high-side drivers are supplied directly by the charge pump. All drivers are
designed to operate at switching frequencies in the range of DC up to 50kHz. The maximum
gate charge that can be delivered to each external Power-NMOS transistor at 50kHz is 100nC.
The output drivers are directly controlled by the digital input pins IL1 to IL3 and IH1 to IH3 (see
Table
drivers properly the following requirements have to be fulfilled:
If a short circuit is detected by one of the sense inputs S1 to S3, the output drivers will be
switched off after a debounce time of 6 µs and the output DG1 will be flagged (see also
tion 3.8 “Short Circuit Detection” on page
DG1 will be cleared with a rising edge at one of the control inputs (IL1 to IL3, IH1 to IH3).
Additional logic prevents short circuits due to switching on one power-NMOS transistor while
the opposite one in the same branch is switched on already.
Table 3-1.
1. Device is in Active Mode.
2. In case of watchdog is enabled, at least one valid watchdog trigger has been
3. The voltage at pin PBAT lies within its operation range. Neither undervoltage nor
4. The charge pump output voltage has been accepted as good, thus it exceeded
5. No overtemperature shutdown has occurred.
Active
Active
Active
Active
Mode
Sleep
accepted.
overvoltage is present.
VCP
3-1). All pins are equipped with an internal pull-down resistor. To operate the output
CPGOOD
Status of the Output Drivers Depending on the Control Inputs
Control
IL(1..3)
Inputs
.
X
0
1
0
1
Control
IH(1..3)
Inputs
X
0
0
1
1
Driver Stage for External
L(1..3) ON, H(1..3) OFF
H(1..3) ON, L(1..3) OFF
11). The output drivers will be enabled again and
L(1..3), H(1..3)
Power MOS
OFF
OFF
OFF
Shoot-through protection
Sleep Mode
Comments
9122G–AUTO–10/10
Sec-