ISL6580CR Intersil, ISL6580CR Datasheet - Page 22

• Manufacturer Part Number: ISL6580CR
• Description: IC DRIVER HIGH SIDE FET 56-QFN
• Manufacturer: Intersil
• Type: High Side/Low Side Driverr

Specifications of ISL6580CR

• Input Type: Non-Inverting
• Number Of Outputs: 12
• On-state Resistance: 20 mOhm
• Current - Output / Channel: 25A
• Current - Peak Output: 35A
• Voltage - Supply: 5 V ~ 12 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The key characteristic for the low side MOSFET is the DC
Rdson resistance. It is important to get a very low Rdson
value for the low side FET. For the high side MOSFET, gate
charge requirements are the key characteristic. Large gate
charge and gate resistance increases switching losses.
Because the high side MOSFET is integrated within the
ISL6580, a very low gate resistance of less then 300mW is
present. In a discrete high side MOSFET solution, a typical
total gate resistance from the gate driver and including the
internal silicon gate resistance is 1.5 to 2W. The integrated
MOSFET in the ISL6580 is optimized for high switching
efficiency with a low gate capacitance.
Understanding the turn on and turn off event for a MOSFET
is important in understanding how to interpret a data sheet
and for troubleshooting methods for the low side MOSFET in
particular.
Switching of the MOSFET
The MOSFET is driven by the applied gate to source
voltage. When the gate voltage is initially applied, the voltage
FIGURE 34. POWER DISSIPATION FOR STATIC AND DYNAMIC
FIGURE 35. MOSFET TURN ON CURVES
OPERATION
22
ISL6580
potential begins to ramp across the gate to the source, but
no current flows until the intrinsic threshold voltage level is
achieved (Figure 35). During time t1, the gate to source
capacitance (C
(I
The slope of the current is directly related to the gate voltage
rise time and the forward transconductance of the device as
follows:
where:
IC = Drain Current
gm = Forward Transconductance
V
The gate to source voltage ramp during this time is:
where:
V
V
R
Ciss = Constant Input Capacitance
V
I
gm = Forward Transconductance
Substituting equation 7 into equation 6 gives:
Once time t2 is reached, C
plateaus and V
gate to drain capacitance (C
capacitance, begins to charge. Once the Miller capacitance
is fully charged, V
the gate supply.
V
C
dI
-------- -
dV
-------------- -
dI
-------- -
DS
dt
DS
DS
GG
TH
G
dt
plateau
C
dt
= Collector Current
C
DS
= Gate Resistance
) and gate to source voltage (V
=
= Drain to Source Voltage
= Drain to Source Voltage
= Threshold Voltage
= Gate Supply Voltage
=
gm
=
gm
V
----------------------------------------- -
=
dV
-------------- -



GG
V
----------------------------------------- -
V
dt
R
DS
GG
TH
G
–
R
GS
DS
–
V
G
+
–
plateau
C
GS
–
--------
gm
) charges and the drain to source current
V
I
iss
begins to ramp down. During time t2, the
C
C
plateau
ies
rises until it reaches the voltage level of



GS
GD
has been fully charged. IDS
), also known as the Miller
GS
) continue to ramp.
(EQ. 6)
(EQ. 7)
(EQ. 8)
(EQ. 9)