IXDR502D1B IXYS, IXDR502D1B Datasheet - Page 4

• Manufacturer Part Number: IXDR502D1B
• Description: IC GATE LS DRVR SGL 2A 6-DFN
• Manufacturer: IXYS
• Type: Low Sider

Specifications of IXDR502D1B

• Input Type: Inverting
• Number Of Outputs: 1
• On-state Resistance: 4 Ohm
• Current - Output / Channel: 500mA
• Current - Peak Output: 2A
• Voltage - Supply: 4.5 V ~ 25 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 6-DFN
• Rise Time: 12 ns
• Fall Time: 10 ns
• Supply Voltage (min): 4.5 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Number Of Drivers: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Copyright © 2007 IXYS CORPORATION All rights reserved
*
1) The θ
by the resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with
vertical boards and the values would be lower with forced convection. For the 6-Lead DFN package, the θ
package is soldered on a PCB. The θ
provides a low thermal resistance to the die, it is easy to reduce the θ
These can reduce the θ
management will vary significantly with size, construction, layout, materials, etc. This typical range tells the user what they are likely
to get if no thermal management is done.
2) θ
not published for the PDIP and SOIC packages. The θ
junction to the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The θ
heatsink. The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily
available IMS in the U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was
assumed. The result was given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential
low thermal resistance for the DFN package.
Unless otherwise noted, 4.5V ≤ V
All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions.
Electrical Characteristics @ temperatures over -55
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
Symbol
V
V
V
I
V
V
R
R
I
t
t
t
t
V
I
IN
DC
R
F
ONDLY
OFFDLY
CC
The following notes are meant to define the conditions for the θ
IH
IL
IN
OH
OL
CC
OH
OL
reliability.
to highlight any specific performance limits within which the device is guaranteed to function.
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
J-C
(max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θ
J-A
J-S
(typ) is defined as junction to ambient. The θ
(typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a
Parameter
High input voltage
Low input voltage
Input voltage range
Input current
High output voltage
Low output voltage
Output resistance
@ Output high
Output resistance
@ Output Low
Continuous output
current
Rise time
Fall time
On-time propagation
delay
Off-time propagation
delay
Power supply voltage
Power supply current
J-A
(typ) to 125 ° C/W easily, and potentially even lower. The θ
CC
≤ 22V , Tj < 150
J-A
(typ) is 200 ° C/W with no special provisions on the PCB, but because the center pad
Test Conditions
4.5V ≤ V
4.5V ≤ V
0V ≤ V
V
V
C
C
C
C
V
V
V
CC
CC
IN
IN
IN
L
L
L
L
=1000pF Vcc=15V
=1000pF Vcc=15V
=1000pF Vcc=15V
=1000pF Vcc=15V
o
= + V
C
= 3.5V
= 0V
= 15V
= 15V
IN
J-C
CC
CC
≤ V
CC
J-A
for the DFN packages are important to show the low thermal resistance from
, (4.5V≤ V
≤ 15V
≤ 15V
CC
of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated
J-A
4
, θ
J-C
CC
J-A
and θ
≤ 18V)
by adding connected copper pads or traces on the PCB.
o
C to 125
J-S
values:
V
CC
J-A
Min
3.5
-20
4.5
-5
- 0.05
for DFN on PCB without heatsink or thermal
IXDR502 / IXDS502
o
C
(3)
Typ
15
1
0
J-A
value supposes the DFN
V
J-C
CC
Max
0.05
0.8
0.3
values are generally
20
22
10
10
14
12
40
35
6
4
3
+ 0.3
Units
mA
µA
µA
µA
ns
ns
ns
ns
Ω
Ω
V
V
V
V
V
A
V