ADP3121JRZ-RL ON Semiconductor, ADP3121JRZ-RL Datasheet
ADP3121JRZ-RL
Specifications of ADP3121JRZ-RL
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ADP3121JRZ-RL Summary of contents
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... WW = Work Week PIN ASSIGNMENT BST ORDERING INFORMATION Device Package ADP3121JRZ−RL SOIC_N (Pb−Free) ADP3121JCPZ−RL LFCSP_VD (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 Publication Order Number: ...
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ADP3121 IN 2 CMP 1V DELAY OD 3 PIN DESCRIPTION Pin No. Pin Name 1 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high−side MOSFET while it ...
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MAXIMUM RATINGS Rating q , SOIC_N JA 2−Layer Board 4−Layer Board , LFCSP_VD (Note 4−Layer Board Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 ...
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ELECTRICAL CHARACTERISTICS Characteristic SUPPLY Supply Voltage Range Supply Current BST = INPUTS Input Voltage High Input Voltage Low Input Current Hysteresis PWM INPUTS Input Voltage High Input Voltage Low Input Current Hysteresis HIGH−SIDE ...
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Theory of Operation The ADP3121 is optimized for driving two N−channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high side and the low−side MOSFETs. Each driver ...
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Re−arranging Equation 1 and Equation 2 to solve for C yields: BST1 Q GATE BST1 can then be found by rearranging Equation 1. BST2 Q GATE BST2 ...
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... Miller−to−input capacitance ratio is low enough, and that the low−side MOSFET internal delays are not so large as to allow accidental turn−on of the low−side when the high−side turns on. Contact ON Semiconductor for an updated list of recommended low−side MOSFETs. PC Board Layout Considerations ...
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OD t pdlOD DRVH OR DRVL Figure 3. Output Disable Timing Diagram fDRVL pdlDRVL DRVL t pdhDRVH DRVH− pdhOD 90% 10% t pdlDRVH t t fDRVH rDRVH V TH Figure 4. Timing Diagram http://onsemi.com 8 ...
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... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...
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... PACKAGE OUTLINE 0.50 PITCH *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...