NCP3418ADR2 ON Semiconductor, NCP3418ADR2 Datasheet
NCP3418ADR2
Specifications of NCP3418ADR2
Related parts for NCP3418ADR2
NCP3418ADR2 Summary of contents
Page 1
NCP3418, NCP3418A Dual Bootstrapped 12 V MOSFET Driver with Output Disable The NCP3418 and NCP3418A are dual MOSFET gate drivers optimized to drive the gates of both high- -side and low- -side power MOSFETs in a synchronous buck converter. Each ...
Page 2
... ORDERING INFORMATION Device NCP3418D NCP3418DR2 NCP3418DR2G NCP3418ADR2 NCP3418ADR2G NCP3418PDR2 NCP3418APDR2 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ PIN DESCRIPTION Pin Symbol 1 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this boot- strap voltage for the high--side MOSFET switched ...
Page 3
MAXIMUM RATINGS Operating Ambient Temperature Operating Junction Temperature, T (Note 1) J Package Thermal Resistance: SO--8 Junction--to--Case, R θJC Junction--to--Ambient, R (2--Layer Board) θJA Package Thermal Resistance: SO--8 EP Junction--to--Ambient, R (Note 2) θJA Storage Temperature Range, T ...
Page 4
NCP3418- -SPECIFICATIONS (Note 5) (V Parameter SUPPLY Supply Voltage Range Supply Current OD INPUT Input Voltage High Input Voltage Low Input Current Propagation Delay Time (Note 6) PWM INPUT Input Voltage High Input Voltage Low Input Current HIGH- -SIDE DRIVER ...
Page 5
OD t pdlOD DRVH or DRVL IN t pdlDRVL DRVL 90% 1.5 V DRVH--SW SW Figure 3. Nonoverlap Timing Diagram (timing is referenced to the 90% and 10% points unless otherwise noted) 90% Figure 2. Output Disable Timing Diagram t ...
Page 6
IN DRVH DRVL Figure 4. DRVH Rise and DRVL Fall Times 40 30 trTG 20 trBG LOAD CAPACITANCE (nF) Figure 6. Rise Time vs. Load Capacitance Figure ...
Page 7
Theory of Operation The NCP3418 and NCP3418A are single phase MOSFET drivers optimized for driving two N- -channel MOSFETs in a synchronous buck converter topology. The NCP3418 features an internal diode, while the NCP3418A requires an external BST diode for ...
Page 8
... S B 0.25 (0.010 - SEATING PLANE - - 0.25 (0.010 *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC CASE 751--07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 ...
Page 9
... SIDE VIEW C 0.275 *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein ...