ISL6614ACB Intersil, ISL6614ACB Datasheet - Page 8

• Manufacturer Part Number: ISL6614ACB
• Description: IC DRIVER MOSF DUAL SYNC 14SOIC
• Manufacturer: Intersil

Specifications of ISL6614ACB

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 10.0ns
• Current - Peak: 1.25A
• Number Of Configurations: 2
• Number Of Outputs: 4
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 10.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Description
Operation
Designed for versatility and speed, the ISL6614A MOSFET
driver controls both high-side and low-side N-Channel FETs of
two half-bridge power trains from two externally provided PWM
signals.
Prior to VCC exceeding its POR level, the Pre-POR
overvoltage protection function is activated during initial startup;
the upper gate (UGATE) is held low and the lower gate
(LGATE), controlled by the Pre-POR overvoltage protection
circuits, is connected to the PHASE. Once the VCC voltage
surpasses the VCC Rising Threshold (See “Electrical
Specifications” table on page 5), the PWM signal takes control
of gate transitions. A rising edge on PWM initiates the turn-off of
the lower MOSFET (see “TIMING DIAGRAM” on page 8). After
a short propagation delay [t
Typical fall times [t
Specifications” table on page 6. Adaptive shoot-through
circuitry monitors the PHASE voltage and determines the upper
gate delay time [t
upper MOSFETs from conducting simultaneously. Once this
delay period is complete, the upper gate drive begins to rise
[t
A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
gate begins to fall [t
circuitry determines the lower gate delay time, t
PHASE voltage and the UGATE voltage are monitored, and
the lower gate is allowed to rise after PHASE drops below a
level or the voltage of UGATE to PHASE reaches a level
depending upon the current direction (See the following
section for details). The lower gate then rises [t
the lower MOSFET.
RU
] and the upper MOSFET turns on.
PWM
UGATE
LGATE
t
PDLL
PDHU
FL
FU
PDLU
] are provided in the “Electrical
]. Again, the adaptive shoot-through
]. This prevents both the lower and
] is encountered before the upper
PDLL
t
FL
8
], the lower gate begins to fall.
t
PDHU
t
RU
t
PDHL
RL
PDHL
], turning on
t
RL
FIGURE 1. TIMING DIAGRAM
t
. The
PDLU
t
FU
ISL6614A
1.5V<PWM<3.2V
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
These drivers incorporate a unique adaptive deadtime control
technique to minimize deadtime, resulting in high efficiency
from the reduced freewheeling time of the lower MOSFETs’
body-diode conduction, and to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.2V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released
to rise. An auto-zero comparator is used to correct the
r
detection of the -0.2V phase level during r
period. In the case of zero current, the UGATE is released
after 35ns delay of the LGATE dropping below 0.5V. During
the phase detection, the disturbance of LGATE’s falling
transition on the PHASE node is blanked out to prevent falsely
tripping. Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn on.
Three-State PWM Input
A unique feature of these drivers and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the driver outputs are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the “Electrical Specifications” table on
DS(ON)
t
TSSHD
drop in the phase voltage preventing from false
t
PDTS
1.0V<PWM<2.6V
t
TSSHD
DS(ON)
conduction
t
PDTS
May 5, 2008
FN9160.4