A3940KLP Allegro Microsystems Inc, A3940KLP Datasheet - Page 10

• Manufacturer Part Number: A3940KLP
• Description: IC CTRLR MOSFET FULL 28TSSOP
• Manufacturer: Allegro Microsystems Inc

Specifications of A3940KLP

• Configuration: H Bridge
• Input Type: Non-Inverting
• Delay Time: 225ns
• Current - Peak: 700mA
• Number Of Configurations: 1
• Number Of Outputs: 4
• Voltage - Supply: 7 V ~ 40 V
• Operating Temperature: -40°C ~ 135°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• High Side Voltage - Max (bootstrap): -

Motor Lead Protection. A fault detection circuit monitors
the voltage across the drain to source of the external MOSFETs.
A fault is asserted “high” on the output terminal, FAULT, if the
drain-to-source voltage of any MOSFET that is instructed to turn
on is greater than the voltage applied to the V
When a high-side switch is turned on, the voltage from V
the appropriate motor phase output, V
motor lead is shorted to ground the measured voltage will
exceed the threshold and the FAULT terminal will go “high”.
Similarly, when a low-side MOSFET is turned on, the differen-
tial voltage between the motor phase (drain) and the LSS
terminal (source) is monitored. V
to V
fault circuitry will wait two dead times after every PWM/phase
change before monitoring the drain-to-source voltage; except, it
will use one dead time for (1) a long coast to any phase on, or
(2) a long hi-Z before on for that phase. This allows time for the
motor output voltage to settle before checking for motor fault
when using slow rise/fall gate-control waveforms.
high-side, drain-source monitor circuit. Voltage drops across
the power bus are eliminated by connecting an isolated PCB
trace from the V
bridge. This allows improved accuracy in setting the V
threshold voltage. The low-side, drain-source monitor uses the
LSS terminal, rather than V
Fault States. The FAULT terminal provides real time
indication of fault conditions after some digital noise filtering.
The V
every motor phase. Bridge (or motor) faults are latched but
cleared by a RESET = 0 pulse or by power cycling. GHx = GLx
= 0 during RESET = 0. The undervoltage, overvoltage, and
thermal shutdown faults are not latched and will not reset until
the cause is eliminated. All faults cause, via the FAULT line, a
coast and some cause shutdown of the regulators, as in the Fault
Responses table (next page).
Note: As a test mode, if the thermal shutdown or SLEEP has not
occurred and the FAULT output is externally held low, the coast
mode and regulator shutdowns will not occur if motor or voltage
faults occur. Do not wire-OR this terminal to other FAULT
lines.
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REG5
To prevent erroneous motor faults during switching, the
The V
DRAIN
.
DRAIN
fault acts as if a short-to-ground fault existed on
is intended to be a Kelvin connection for the
DRAIN
terminal to the drain of the MOSFET
DRAIN
, in comparing against V
DSTH
SX
is set by a resistor divider
, is examined. If the
DSTH
input terminal.
Functional Description
DSTH
DRAIN
DSTH
.
to
Dead Time. The A3940 is intended to drive a wide range of
power MOSFETs in applications requiring a wide range of
switching times. In order to prevent cross conduction (a.k.a.
shoot-through) during direction and PWM changes, a power
MOSFET must be turned off before its “phase-pin mate” is
turned on.
where K = 1 for LONG = 0; K = 32 for LONG = 1.
Note: I
Sleep Mode. RESET = 0 clears any latched motor faults
while driving all gate drive outputs low (coast). Eventually,
RESET = 0 turns off all circuits to allow minimum current draw.
GHx and GLx outputs go high impedance (Z) when V
4 V. RESET = 1 enables the device after it powers up all
circuits. The user should wait the pump-up time,
device to be powered up properly before a gate output is
enabled. Please refer to power-up diagram in application note
AN295040 for more detail.
Charge Pump. The A3940 is designed to accommodate a
wide range of power supply voltages. The charge pump output
voltage, V
V
VREG13. A 13.3 V, low-dropout, linear regulator is used to
power the low-side gate drive circuit directly and to provide the
current to charge the bootstrap capacitors for the high-side gate
drive. The input supply connection to this regulator, VIN, can
be externally connected to the charge pump output, VCP, or it
can be directly connected to the VBB or VBAT terminal.
Internal current limiting protects V
VREG5. A 5 V, low-dropout, linear regulator is used to power
the internal logic, regulators, and thermal detection. This
regulator can also power low-current external resistor networks
for VDSTH and OVSET, and the FAULT output pull-up. The
input supply connection is VBB. Internal current limiting
protects V
Power-Up State. If the input logic is open, internal pull-
downs put the system in coast mode on powering up. First, issue
a brake command for >10 µs to charge the bootstrap capacitors
and avoid a possible short-to-ground fault indication.
BB
< 11 V).
DEAD
CP
REG5
t
(mA) ≈ 2/R
DEAD
, is regulated to V
.
(ns) = K([18.8R
MOSFET CONTROLLER
FULL-BRIDGE POWER
DEAD
(kΩ), 12 kΩ<R
BB
DEAD
+ 11 V (or about 2V
REG13
(kΩ)] + 50) + 90
.
DEAD
<500 kΩ.
t
up
,
3940
to allow the
BB
REG13
if
<
9