ISL6615CBZ-T Intersil, ISL6615CBZ-T Datasheet - Page 9

• Manufacturer Part Number: ISL6615CBZ-T
• Description: IC MOSFET DRVR SYNC HF 6A 8-SOIC
• Manufacturer: Intersil

Specifications of ISL6615CBZ-T

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 10.0ns
• Current - Peak: 2.5A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 6.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• Shorten all gate drive loops (UGATE-PHASE and
• Minimize the inductance of the PHASE node. Ideally, the
• Minimize the current loop of the output and input power
• Avoid routing relatively high impedance nodes (such as
In addition, for heat spreading, place copper underneath the
IC whether it has an exposed pad or not. The copper area
can be extended beyond the bottom area of the IC and/or
connected to buried power ground plane(s) with thermal
vias. This combination of vias for vertical heat escape,
extended copper plane, and buried planes for heat
spreading allows the IC to achieve its full thermal potential.
Upper MOSFET Self Turn-On Effects at Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to the
self-coupling via the internal C
UGATE could momentarily rise up to a level greater than the
threshold voltage of the MOSFET. This could potentially turn
on the upper switch and result in damaging inrush energy.
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is a common practice to
place a resistor (R
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the C
threshold of the upper MOSFET. A higher dV/dt, a lower
LGATE-GND) and route them closely spaced.
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
trains. Short the source connection of the lower MOSFET
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be
placed as close to the drain of upper and source of lower
MOSFETs as possible.
PWM and ENABLE lines) close to high dV/dt UGATE and
PHASE nodes.
GD
UGPH
/C
GS
) across the gate and source of the
ratio, as well as the gate-source
9
GD
of the MOSFET, the
ISL6615
C
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20kΩ typically sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated with the
formulas in Equation 5, which assume a fixed linear input
ramp and neglect the clamping effect of the body diode of
the upper drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purpose only.
Therefore, the actual coupling effect should be examined
using a very high impedance (10MΩ or greater) probe to
ensure a safe design margin.
V
DS
R
GS_MILLER
FIGURE 5. GATE-TO-SOURCE RESISTOR TO REDUCE
PVCC
=
/C
R
GS
UGPH
ratio, and a lower gate-source threshold upper
UPPER MOSFET MILLER COUPLING
=
+
DU
DL
R
dV
------- R C
dt
GI
⋅
⋅
C
PHASE
BOOT
UGATE
rss
rss
C
⎛
⎜
⎜
⎜
⎜
⎝
BOOT
1 e
=
–
C
--------------------------------- -
dV
------ - R C
GD
dt
G
–
⋅
V
DS
R
⋅
C
GI
GD
iss
C
C
⎞
⎟
⎟
⎟
⎟
⎠
iss
GS
S
=
VIN
C
Q
GD
April 24, 2008
UPPER
D
(EQ. 5)
+
FN6481.0
C
C
DS
GS