SI8220CD-A-ISR Silicon Laboratories Inc, SI8220CD-A-ISR Datasheet - Page 15
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SI8220CD-A-ISR
Manufacturer Part Number
SI8220CD-A-ISR
Description
IC ISODRIVER 2.5A OPTO IN 16SOIC
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI8220CB-A-ISR.pdf
(30 pages)
Specifications of SI8220CD-A-ISR
Configuration
Isolated
Input Type
Opto
Delay Time
50ns
Current - Peak
2.5A
Number Of Configurations
1
Number Of Outputs
2
Voltage - Supply
6.5 V ~ 24 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
High Side Voltage - Max (bootstrap)
-
6. Applications
6.1. Power Supply Connections
V
24 V. V
for these capacitors depend on load current and the distance between the chip and its power source. It is
recommended that 0.1 and 10 µF bypass capacitors be used to reduce high-frequency noise and maximize
performance.
6.2. Layout Considerations
It is most important to minimize ringing in the drive path and noise on the V
minimize parasitic inductance in these paths by locating the Si8220/21 as close to the device it is driving as
possible. In addition, the V
and ground planes is highly recommended. A split ground plane system having separate ground and V
for power devices and small signal components provides the best overall noise performance.
6.3. Power Dissipation Considerations
Proper system design must assure that the Si8220/21 operates within safe thermal limits across the entire load
range. The Si8220/21 total power dissipation is the sum of the power dissipated by bias supply current, internal
switching losses, and power delivered to the load, as shown in Equation 1.
The maximum allowable power dissipation for the Si8220/21 is a function of the package thermal resistance,
ambient temperature, and maximum allowable junction temperature, as shown in Equation 2.
Substituting values for P
dissipation of 1.0 W. The maximum allowable load is found by substituting this limit and the appropriate datasheet
values from Table 1 on page 4 into Equation 1 and simplifying. The result is Equation 3, where V
I
F
SS
= 10 mA, and V
can be biased at, above, or below ground as long as the voltage on V
DD
decoupling capacitors should be placed as close to the package pins as possible. The optimum values
DD
P
where:
P
I
V
I
C
V
F is the switching frequency (Hz)
F
QOUT
D
= 18 V.
D
F
int
DD
is the diode current (20 mA max)
P
where:
P
T
T
is the diode anode voltage (2.8 V max)
is the total Si8220 device power dissipation (W)
=
ja
Dmax
jmax
A
is the internal parasitic capacitance (370 pF)
Dmax
is the driver-side supply voltage (24 V max)
is the ambient temperature (°C)
Dmax
is the Si8220/21 package junction-to-air thermal resistance (125 °C/W)
is the driver maximum bias curent (5 mA)
V
DD
F
is the Si8220/21 maximum junction temperature (150 °C)
I
is the maximum allowable Si8220/21 power dissipation (W)
Duty Cycle
supply and ground trace paths must be kept short. For this reason, the use of power
T
---------------------------
F
T
jmax
jmax
ja
–
, T
T
A
A
, and
+
V
DD
ja
Equation 1.
Equation 2.
I
into Equation 2 results in a maximum allowable total power
Rev. 1.0
QOUT
+
C
int
V
DD
2
F
DD
+
with respect to V
C
DD
L
V
lines. Care must be taken to
DD
2
F
Si8220/21
SS
is a maximum of
DD
F
= 2.8 V,
planes
15