PX3511BDAG Intersil, PX3511BDAG Datasheet - Page 7

• Manufacturer Part Number: PX3511BDAG
• Description: IC DRVR SYNC BUCK HF 8-SOIC
• Manufacturer: Intersil

Specifications of PX3511BDAG

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 10.0ns
• Current - Peak: 1.25A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 10.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

input oscillations due to the capacitive load seen by the
PWM input through the body diode of the controller’s PWM
output when the power-up and/or power-down sequence of
bias supplies of the driver and PWM controller are required.
Power-On Reset (POR) Function
During initial startup, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 9.8V (typically),
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold of 7.6V (typically), operation of the driver is
disabled.
Pre-POR Overvoltage Protection
Prior to VCC exceeding its POR level, the upper gate is held
low and the lower gate is controlled by the overvoltage
protection circuits during initial startup. The PHASE is
connected to the gate of the low side MOSFET (LGATE),
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during initial startup. For
complete protection, the low side MOSFET should have a
gate threshold well below the maximum voltage rating of the
load/microprocessor.
When VCC drops below its POR level, both gates pull low
and the Pre-POR overvoltage protection circuits are not
activated until VCC resets.
Internal Bootstrap Device
Both drivers feature an internal bootstrap schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above UVCC + 5V and its capacitance value can be
chosen from the following equation:
where Q
at V
control MOSFETs. The ΔV
allowable droop in the rail of the upper gate drive.
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, Q
sheet is 10nC at 4.5V (V
Q
PX3511B, VCC in PX3511A) = 12V. We will assume a
C
Q
GATE
BOOT_CAP
GATE
GS1
=
is calculated to be 53nC for UVCC (i.e. PVCC in
G1
gate-source voltage and N
Q
----------------------------------- - N
G1
is the amount of gate charge per upper MOSFET
≥
V
------------------------------------- -
ΔV
•
GS1
UVCC
BOOT_CAP
Q
GATE
•
GS
Q1
BOOT_CAP
) gate-source voltage. Then the
7
Q1
term is defined as the
is the number of
G
, from the data
PX3511A, PX3511B
(EQ. 1)
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.267μF is required.
Gate Drive Voltage Versatility
The PX3511A and PX3511B provide the user flexibility in
choosing the gate drive voltage for efficiency optimization.
The PX3511A upper gate drive is fixed to VCC [+12V], but
the lower drive rail can range from 12V down to 5V
depending on what voltage is applied to PVCC. The
PX3511B ties the upper and lower drive rails together.
Simply applying a voltage from 5V up to 12V on PVCC sets
both gate drive rail voltages simultaneously.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
the SO8 package is approximately 800mW at room
temperature, while the power dissipation capacity in the DFN
package with an exposed heat escape pad is more than
1.5W. The DFN package is more suitable for high frequency
applications. See Layout Considerations paragraph for
thermal transfer improvement suggestions. When designing
the driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
1.6
1.4
1.2
0.8
0.6
0.4
0.2
0.0
1.
0.0
20nC
0.1
VOLTAGE
0.2
50nC
Q
GATE
SW
0.3
), the output drive impedance, the
= 100nC
ΔV
0.4
BOOT_CAP
0.5
0.6
(V)
0.7
0.8
February 26, 2007
0.9
FN6462.0
1.0