ADP3624ARDZ Analog Devices Inc, ADP3624ARDZ Datasheet
ADP3624ARDZ
Specifications of ADP3624ARDZ
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ADP3624ARDZ Summary of contents
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ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 FEATURES Industry-standard-compatible pinout High current drive capability Precise threshold shutdown comparator UVLO with hysteresis Overtemperature warning signal Overtemperature shutdown 3.3 V-compatible inputs 10 ns typical rise time and fall time @ 2.2 nF load Matched propagation delays between channels ...
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ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing ....................................................... Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and ...
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SPECIFICATIONS −40°C to +125°C, unless otherwise noted Table 1. Parameter SUPPLY Supply Voltage Range Supply Current Standby Current UVLO Turn-On Threshold Voltage Turn-Off Threshold Voltage Hysteresis DIGITAL INPUTS (INA, INA, INB, INB, ...
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ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 TIMING SD OUTA, OUTB V INA, IH INB OUTA, OUTB INA INB OUTA, OUTB V UVLO_ON V UVLO_OFF V DD UVLO MODE OUTPUTS DISABLED t dL_SD 90% Figure 2. Shutdown Timing Diagram RISE 90% ...
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ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 NORMAL OPERATION OT WARNING OT SHUTDOWN OUTPUTS OUTPUTS ENABLED DISABLED OTW Figure 6. Overtemperature Warning and Shutdown Rev Page – SD HYS_SD T T – W ...
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ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDD OUTA, OUTB DC <200 ns INA, INA, INB, INB, and SD ESD Human Body Model (HBM) Field Induced Charged Device Model (FICDM) SOIC_N_EP MINI_SO_EP θ , JEDEC 4-Layer Board JA 1 SOIC_N_EP ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 3. ADP3623/ADP3633 Pin Function Descriptions Pin No. Mnemonic Description 1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. 2 INA Inverting Input Pin for Channel A Gate ...
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ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 Table 5. ADP3625/ADP3635 Pin Function Descriptions Pin No. Mnemonic Description 1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. 2 INA Inverting Input Pin for Channel A Gate Driver. 3 PGND Ground. ...
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TYPICAL PERFORMANCE CHARACTERISTICS 9 V UVLO_ON 8 V UVLO_OFF 7 ADP3633/ADP3634/ADP3635 6 5 ADP3623/ADP3624/ADP3625 V UVLO_ON 4 V UVLO_OFF 3 –50 –30 – TEMPERATURE (°C) Figure 10. UVLO vs. Temperature FALL 10 t RISE ...
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ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 OUTA/OUTB 2 INA/INB V = 12V DD 1 TIME = 20ns/DIV Figure 16. Typical Rise Propagation Delay (Noninverting) OUTA/OUTB 2 INA/INB V = 12V DD 1 TIME = 20ns/DIV Figure 17. Typical Fall Propagation Delay (Noninverting Figure ...
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TEST CIRCUIT ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 ADP3623/ADP3624/ADP3625 ADP3633/ADP3634/ADP3635 1 OTW 8 SD NONINVERTING INA, A INA OUTA 2 7 INVERTING V DD PGND VDD 3 6 4.7µF NONINVERTING CERAMIC B INB, INB OUTB 4 5 INVERTING Figure 20. Test Circuit Rev ...
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ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 THEORY OF OPERATION The ADP362x/ADP363x family of dual drivers is optimized for driving two independent enhancement N-channel MOSFETs or insulated gate bipolar transistors (IGBTs) in high switching frequency applications. These applications require high speed, fast rise and fall times, ...
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VDD OTW ADP3623/ADP3624/ADP3625/ ADP3633/ADP3634/ADP3635 PGND VDD OTW ADP3623/ADP3624/ADP3625/ ADP3633/ADP3634/ADP3635 PGND Figure 23. OTW Signaling Scheme Example OTW The open-drain configuration allows connection of multiple devices to the same warning bus in a wire-OR’ configuration, as shown in Figure ...
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ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 THERMAL CONSIDERATIONS When designing a power MOSFET gate drive, the maximum power dissipation in the driver must be considered to avoid exceeding maximum junction temperature. Data on package thermal resistance is provided in Table 2 to help the designer ...
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OUTLINE DIMENSIONS 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) MAX COPLANARITY 0.10 CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN ...
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... Range 1 ADP3623ARDZ-RL 4.5 V −40°C to +85°C 1 ADP3623ARHZ-RL 4.5 V −40°C to +85°C 1 ADP3624ARDZ 4.5 V −40°C to +85°C 1 ADP3624ARDZ-RL 4.5 V −40°C to +85°C 1 ADP3624ARHZ 4.5 V −40°C to +85°C 1 ADP3624ARHZ-RL 4.5 V −40°C to +85°C 1 ADP3625ARDZ-RL 4.5 V −40°C to +85°C ...