IR2166STRPBF International Rectifier, IR2166STRPBF Datasheet - Page 21

• Manufacturer Part Number: IR2166STRPBF
• Description: IC PFC BALLAST CTLR 16-SOIC
• Manufacturer: International Rectifier
• Type: PFC/Ballast Controllerr

Specifications of IR2166STRPBF

• Frequency: 39 ~ 50 kHz
• Current - Supply: 10mA
• Current - Output: 400mA
• Voltage - Supply: 11.5 V ~ 15.6 V
• Operating Temperature: -25°C ~ 125°C
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Ignition Mode (IGN)
The ignition mode is defined as the state the IC
is in when a high voltage is being established
across the lamp necessary for igniting the lamp.
The IR2166 enters ignition mode when the
voltage on pin CPH exceeds 10V.
Pin CPH is connected internally to the gate of a
P-channel MOSFET (S4) (see Figure 4) that
connects pin RPH with pin RT. As pin CPH
exceeds 10V, the gate-to-source voltage of
MOSFET S4 begins to fall below the turn-on
threshold of S4. As pin CPH continues to ramp
towards VCC, switch S4 turns off slowly. This
results in resistor RPH being disconnected
smoothly from resistor RT, which causes the
operating frequency to ramp smoothly from the
preheat frequency, through the ignition frequency,
to the final run frequency. The over-current
threshold on pin CS will protect the ballast
against a non-strike or open-filament lamp fault
condition. The voltage on pin CS is defined by
the lower half-bridge MOSFET current flowing
through the external current sensing resistor
RCS. The resistor RCS therefore programs the
maximum allowable peak ignition current (and
therefore peak ignition voltage) of the ballast
output stage. If the number of over current pulses
exceed 25, the IC will enter fault mode and gate
driver outputs HO, LO and PFC will be latched
low.
Run Mode (RUN)
Once the lamp has successfully ignited, the
ballast enters run mode. The run mode is defined
as the state the IC is in when the lamp arc is
established and the lamp is being driven to a
given power level. The run mode oscillating
frequency is determined by the timing resistor
RT and timing capacitor CT (see Design
Equations, page 26, Equations 3 and 4). Should
hard-switching occur at the half-bridge at any
time due to an open-filament or lamp removal,
the voltage across the current sensing resistor,
RCS, will exceed the internal threshold of 1.3 volts
and the IC will enter FAULT mode and gate driver
outputs HO, LO and PFC will be latched low.
DC Bus Under-voltage Reset
Should the DC bus decrease too low during a
brownout line condition or overload condition,
the resonant output stage to the lamp can shift
near or below resonance. This can produce
hard-switching at the half-bridge which can
damage the half-bridge switches or, the DC bus
can decrease too far and the lamp can
extinguish. To protect against this, the VBUS pin
includes a 3.0V under-voltage threshold. Should
the voltage at the VBUS pin decrease below 3.0V,
VCC will be discharged to the UVLO- threshold
and all gate driver outputs will be latched low.
For proper ballast design, the designer should
design the PFC section such that the DC bus
does not drop until the AC line input voltage falls
below the rated input voltage of the ballast (See
PFC section). When correctly designed, the
voltage measured at the VBUS pin will decrease
below the internal 3.0V threshold and the ballast
will turn off cleanly. The pull-up resistor to VCC
( R SUPPLY) will then turn the ballast on again
with the AC input line voltage increasing to the
minimum specified value causing VCC to exceed
UVLO+.
R
the minimum specified ballast input voltage. The
PFC should then be designed such that the DC
bus decreases at an input line voltage that is
SUPPLY
should be set to turn the ballast on at
IR2166 & (PbF)
21