MAX8759ETI+ Maxim Integrated Products, MAX8759ETI+ Datasheet - Page 28

• Manufacturer Part Number: MAX8759ETI+
• Description: IC CNTRL CCFL BACKLIGHT 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: CCFL Controllerr

Specifications of MAX8759ETI+

• Frequency: 30 ~ 80 kHz
• Current - Supply: 2.5mA
• Voltage - Supply: 4.5 V ~ 28 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Lead Free Status / Rohs Status: Details

The transformer core saturation should also be consid-
ered when selecting the operating frequency. The pri-
mary winding should have enough turns to prevent
transformer saturation under all operating conditions.
Use the following expression to calculate the minimum
number of turns N1 of the primary winding:
where D
0.8) of the high-side switches, V
DC input voltage, B
core, and S is the minimal cross-section area of the core.
The COMP capacitor sets the speed of the current loop
that is used during startup, maintaining lamp-current
regulation, and during transients caused by changing
the input voltage. To maintain stable operation, the
COMP capacitor (C
The COMP capacitor also limits the dynamics of the
lamp-current envelope in DPWM operation. At the end of
the DPWM on cycle, the MAX8759 turns on a 110µA
internal current source to linearly discharge the COMP
capacitor. Use the following equation to set the fall time:
where t
and V
is in regulation. At the beginning of the DPWM on cycle,
the COMP capacitor is charged by a transconductance
error amplifier. The rise time is about three times longer
than the fall time.
The TFLT capacitor determines the delay time for both
the open-lamp fault and secondary short-circuit fault.
The MAX8759 charges the TFLT capacitor with a 1µA
current source during an open-lamp fault and charges
the TFLT capacitor with a 135µA current source during
a secondary short-circuit fault. Therefore, the sec-
ondary short-circuit fault delay time is approximately
135 times shorter than that of open-lamp fault. The
MAX8759 sets the fault latch when the TFLT voltage
reaches 4V. Use the following equations to calculate
the open-lamp fault delay (T
ondary short-circuit fault delay (T
Low-Cost, SMBus, CCFL Backlight Controller
28
______________________________________________________________________________________
COMP
FALL
MAX
is the COMP voltage when the lamp current
is the fall time of the lamp-current envelope
is the maximum duty cycle (approximately
C
T
COMP
OPEN LAMP
N
1>
Setting the Fault-Delay Time
S
COMP
_
D
COMP Capacitor Selection
is the saturation flux density of the
=
MAX
B
110µ
S
) needs to be at least 3.3nF.
× ×
V
×
=
S f
COMP
A t
V
C
IN MAX
×
TFLT
MIN
OPEN
(
IN(MAX)
FALL
SEC
1µ
A
× 4
)
_
_
SHORT
LAMP
V
is the maximum
) and sec-
):
The high-side gate drivers are powered using two boot-
strap circuits. The MAX8759 integrates the bootstrap
diodes so only two 0.1µF bootstrap capacitors are
needed. Connect the capacitors (C10 and C11 in
Figure 1) between LX1 and BST1, and between LX2
and BST2 to complete the bootstrap circuits.
The MAX8759 includes two lamp current feedback
input pins that support dual-lamp applications with a
minimum number of external components. Figure 11
shows the typical dual-lamp operating circuit.
Careful PC board layout is important to achieve stable
operation. The high-voltage section and the switching
section of the circuit require particular attention. The
high-voltage sections of the layout need to be well sep-
arated from the control circuit. Most layouts for single-
lamp notebook displays are constrained to long and
narrow form factors, so this separation occurs naturally.
Follow these guidelines for good PC board layout:
1) Keep the high-current paths short and wide, espe-
2) Use a star ground configuration for power and ana-
3) Route high-speed switching nodes away from sensi-
4) Mount the decoupling capacitor from V
5) The current-sense paths for LX1 and LX2 to GND
cially at the ground terminals. This is essential for
stable, jitter-free operation and high efficiency.
log grounds. The power and analog grounds
should be completely isolated—meeting only at the
center of the star. The center should be placed at
the analog ground pin (GND). Using separate cop-
per islands for these grounds can simplify this task.
Quiet analog ground is used for V
FREQ, and TFLT.
tive analog areas (V
Make all pin-strap control input connections to ana-
log ground or V
as close as possible to the IC with dedicated traces
that are not shared with other signal paths.
must be made using Kelvin-sense connections to
guarantee the current-limit accuracy. With 8-pin SO
MOSFETs, this is best done by routing power to the
MOSFETs from outside, using the top copper layer,
while connecting GND and LX inside (underneath)
the 8-pin SO package.
T
SEC SHORT
Dual-Lamp Operating Circuit
CC
_
rather than power ground or V
CC
=
, COMP, FREQ, and TFLT).
Bootstrap Capacitors
C
TFLT
135µ
Layout Guidelines
× 4
A
V
CC
CC
, COMP,
to GND
DD
.