NCP5009DMR2 ON Semiconductor, NCP5009DMR2 Datasheet - Page 9

• Manufacturer Part Number: NCP5009DMR2
• Description: IC LED DRVR WHT BCKLT 10MICROSMD
• Manufacturer: ON Semiconductor
• Type: Backlight, White LEDr

Specifications of NCP5009DMR2

• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 1
• Internal Driver: Yes
• Type - Primary: Backlight
• Type - Secondary: White LED
• Frequency: 5MHz
• Voltage - Supply: 2.7 V ~ 6 V
• Voltage - Output: 15V
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Operating Temperature: -25°C ~ 85°C
• Current - Output / Channel: 75mA
• Internal Switch(s): Yes
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Efficiency: -
• Other names: NCP5009DMR2OSTR

− Qdata is internally set to high level.
− Upon positive going transition of the next CLK signal,
− Clear the Qdata flip−flop upon the positive going of
Remote Control Programming Sequence
sequence will take place:
The sequence keeps going until CS = High.
programming output current flip−flop is set according to
the previous state of the shift register and SetReg B[1−7] is
cleared afterward.
the last SetReg bit will be latched and the output current
Upon CS transition from High to Low, the internal
When the CS line returns to a High state, the
Depending upon the CS width, for a given CLK period,
the Qdata is shifted to the next Bn stage.
the SetReg[B1] transient.
CLEAR
Qdata
I
out ref
CLK
Iout
CS
B1
B2
B3
B4
B5
B6
B7
Output Current Programmed Register
Internal Latch Data and Reset
Figure 19. Programming Sequence
tCSsetup
Last Latched Bit
NCP5008, NCP5009
http://onsemi.com
9
tclear
will be adjusted accordingly. If the number of CLK pulses
is higher than 7, the Qdata is lost and the SetReg register
bits B[1−7] are in the Low state, yielding a zero output
current.
than 7 pulses to the CLK pin when the pin CS is low. If the
internal shift register is clear upon the CS transition from
Low to High, the device will be placed or maintained in the
shut down mode.
is activated and a 100 ms delay (typical) is necessary to
stabilize the output current to the programmed value.
The internal shift register can be clear by sending more
When the register content is higher than zero, the DC/DC
Ioutdly