A6275SLW Allegro Microsystems Inc, A6275SLW Datasheet - Page 7
![IC LED DRIVER LINEAR 16-SOIC](/photos/7/38/73852/mfg_16-soic-7_5mm_sml.jpg)
A6275SLW
Manufacturer Part Number
A6275SLW
Description
IC LED DRIVER LINEAR 16-SOIC
Manufacturer
Allegro Microsystems Inc
Type
Linear (Non-Switching)r
Datasheet
1.A6275SLWTR-T.pdf
(12 pages)
Specifications of A6275SLW
Constant Current
Yes
Topology
8-Bit Shift Register
Number Of Outputs
8
Internal Driver
Yes
Type - Primary
General Purpose
Frequency
20MHz
Voltage - Supply
4.5 V ~ 5.5 V
Voltage - Output
1V
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Operating Temperature
-20°C ~ 85°C
Current - Output / Channel
75.5mA
Internal Switch(s)
Yes
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Efficiency
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A6275SLW
Manufacturer:
ALLEGRO/雅丽高
Quantity:
20 000
A6275
register on the logic 0-to-logic 1 transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data in-
formation towards the SERIAL DATA OUTPUT. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
respective latch when the LATCH ENABLE is high (serial-to-
a p
DATA OUT
OUTPUT
OUTPUT
a r
ENABLE
ENABLE
ENABLE
DATA IN
SERIAL
SERIAL
CLOCK
LATCH
e l l
Serial data present at the input is transferred to the shift
Information present at any register is transferred to the
OUT
OUT
c l
N
N
n o
e v
A
i s r
DATA
n o
. )
50%
B
T
t
e h
p
C
50%
LOW = ALL OUTPUTS ENABLED
t a l
D
50%
h c
50%
F
s e
o c
t
TIMING REQUIREMENTS and SPECIFICATIONS
Serial-Input Constant-Current Latched LED Driver
pHL
t n
50%
HIGH = ALL OUTPUTS DISABLED (BLANKED)
n i
e u
E
90%
with Open LED Detection and Dot Correction
o t
t
p
t
c a
pLH
DATA
e c
(Logic Levels are V
t p
t
DATA
f
e n
50%
w
HIGH = OUTPUT OFF
LOW = OUTPUT ON
t
r
a d
a t
Dwg. WP-030-1A
10%
Dwg. WP-029-1
s a
50%
DATA
o l
the latches are bypassed (LATCH ENABLE tied high) will
e r
data entry.
d
is not affected by the OUTPUT ENABLE input. With the OUT-
PUT ENABLE input low, the outputs are con trolled by the state
f o
DD
i r
g n
u q
e v
h t
and Ground)
r i
When the OUTPUT ENABLE input is high, the output sink
i e
a
s r
t e
t s
r r
a
a h
e h
e r
s e
A. Data Active Time Before Clock Pulse
B. Data Active Time After Clock Pulse
C. Clock Pulse Width, t
D.
E. Latch Enable Pulse Width, t
F. Output Enable Pulse Width, t
NOTE: Timing is representative of a 10 MHz clock. Sig-
n
Max. Clock Transition Time, t
i f i
t t
e p
i d
L
i T
a c
e h
A
a s
i t c
m
t n
T
(Data Set-Up Time), t
(Data Hold Time), t
and Latch Enable, t
l b
e v
e
O
C
y l
d e
B
U
H
a l
i h
e
T
E
(
w t
c t
h g
P
O
N
U
e h
F
e
r e
A
n e
T
F
. s
B
. )
p s
E
C
L
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
T
N
e e
E
o l
h
A
s d
i e
k c
s i
B
w(CK)
e h
f n
L
a
A
su(L)
h(D)
e r
E
r o
t c
d l
su(D)
i
v i
a
m
p n
h
a t t
.................................. 50 ns
................................. 20 ns
............................... 100 ns
i t a
i t a
r
g i
w(L)
t u
or t
n i
w(OE)
. h
............................. 50 ns
n o
n o
b a
e b
A
f
...................... 100 ns
s
. e l
....................... 10 s
p p
i h
o t
................... 4.5 s
h g
e r
c i l
i d
t a
u d
o i
t n
i r
s n
g n
e h
w
s
t a l
e h
r e
h c
l a i
e r
s e
6