ISL97671IRZ Intersil, ISL97671IRZ Datasheet - Page 21

• Manufacturer Part Number: ISL97671IRZ
• Description: IC LED DVR PWM CTRL 6CH 20QFN
• Manufacturer: Intersil

Specifications of ISL97671IRZ

• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 6
• Internal Driver: Yes
• Type - Primary: Automotive, Backlight
• Type - Secondary: RGB, White LED
• Frequency: 600kHz ~ 1.2MHz
• Voltage - Supply: 4.5 V ~ 26.5 V
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 40mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

Device Control Register (0x01)
This register has two bits that control either SMBus/I
controlled or external PWM controlled PWM dimming and
a single bit that controls the BL ON/OFF state. The
remaining bits are reserved. The bit assignment is shown
in Figure 31. All other bits in the Device Control Register
will read as low unless otherwise written.
• All reserved bits have no functional effect when
• All defined control bits return their current, latched
A value of 1 written to BL_CTL turns on the BL in 4ms or
less after the write cycle completes. The BL is
• deemed to be on when Bit 3 BL_STAT of Register 0x02
• A value of 0 written to BL_CTL immediately turns off the
• When SMBus/I
The default value for Register 0x01 is 0x00.
PWM_MD PWM_SEL
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
TABLE 3. OPERATING MODES SELECTED BY DEVICE
RESERVE
written.
value when read.
is 1 and Register 0x09 is not 0.
BL. The BL is deemed to be off when Bit 3 BL_STAT of
Register 0x02 is 0 and Register 0x09 is 0.
Register 0x00 reflects the last value written to it
from SMBus/I
REGISTER 0x01
PWM_MD
X
1
0
D
X
0
0
1
1
CONTROL REGISTER BITS 1 AND 2
RESERVE
1
0
0
PWM_SEL
2
D
2
C.
C mode with DPST is selected,
X
0
1
0
1
PWM Mode
SMBus/I
SMBus/I
DEVICE CONTROL REGISTER
RESERVE
21
FIGURE 31. DESCRIPTIONS OF DEVICE CONTROL REGISTER
D
2
2
BL_CTL
C Mode
C and PWM Mode with DPST
0
1
1
1
1
MODE
RESERVE
D
Backlight Off
SMBus/I
PWMI controlled PWM dimming
SMBus/I
SMBus/I
RESERVE
2
2
2
ISL97671
C and PWM dimming (DPST)
C controlled PWM dimming
C controlled PWM dimming
D
2
C
PWM_MD PWM_SEL
MODE
The PWM_SEL bit determines whether the SMBus/I
PWM input should drive the output brightness in terms of
PWM dimming. When PWM_SEL bit is 1, the PWM drives
the output brightness regardless of what the PWM_MD is.
When the PWM_SEL bit is 0, the PWM_MD bit selects the
manner in which the PWM dimming is to be interpreted;
when this bit is 1, the PWM dimming is based on the
SMBus/I
PWM dimming reflects a percentage change in the
current brightness programmed in the SMBus/I
Register 0x00, i.e. DPST (Display Power Saving
Technology) mode as:
Where:
Cbt = Current brightness setting from SMBus/I
Register 0x00 without influence from the PWM
PWM = is the percent duty cycle of the PWM
For example, the Cbt = 50% duty cycle programmed in
the SMBus/I
tuned to be 200Hz with an appropriate capacitor at the
FPWM pin. On the other hand, PWM is fed with a 1kHz
30% high PWM signal. When PWM_SEL = 0 and
PWM_MD = 0, the device is in DPST operation where
DPST brightness = 15% PWM dimming at 200Hz.
DSPT Brightness
2
C brightness setting. When this bit is 0, the
2
C Register 0x00 and the PWM frequency is
=
Cbt
×
BL_CTL
PWM
June 24, 2010
2
2
C
C
(EQ. 16)
FN7631.0
2
C or