LTC3207EUF#PBF Linear Technology, LTC3207EUF#PBF Datasheet - Page 11

• Manufacturer Part Number: LTC3207EUF#PBF
• Description: IC LED DRIVR QVGA DISPLAY 24-QFN
• Manufacturer: Linear Technology
• Type: QVGA Display (I²C Interface)r

Specifications of LTC3207EUF#PBF

• Topology: Step-Up (Boost), Switched Capacitor (Charge Pump)
• Number Of Outputs: 13
• Internal Driver: Yes
• Type - Primary: Backlight
• Type - Secondary: RGB, White LED
• Frequency: *
• Voltage - Supply: 2.9 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Operating Temperature: -40°C ~ 85°C
• Internal Switch(s): Yes
• Efficiency: 91%
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: QFN EP
• Pin Count: 24
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.9V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Current - Output / Channel: -
• Lead Free Status / Rohs Status: Compliant

SCL
OPERATION
The LTC3207/LTC3207-1 are receive-only (slave) devices.
There are two I
address is 00110110 and the LTC3207-1 I
00110100. The I
the LTC3207 and the LTC3207-1.
Bus Speed
The I
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I
device. It also contains input fi lters designed to suppress
glitches should the bus become corrupt.
SDA
Write Word Protocol Used by the LTC3207/LTC3207-1
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge,
P = Stop Condition
*The sub-address uses only the fi rst four bits, D0, D1, D2 and D3
**Stop can be delayed until all of the data registers have been written
START
1
S Slave Address Wr A *Sub-Address A Data Byte
2
LTC3207
LTC3207-1
C port is designed to be operated at speeds of up
0
0
0
1
7
SDA
SCL
t
HD, STA
0
0
0
2
CONDITION
1
1
1
3
2
START
2
C addresses available. The LTC3207 I
C address is the only difference between
1
ADDRESS
ADDRESS
1
1
1
4
1
0
0
0
5
t
LOW
1
1
1
6
t
r
8
t
1
0
1
7
HIGH
t
SU, DAT
WR
WR
0
0
0
8
t
2
f
1
C compliant master
ACK
9
S7
S7
2
1
8
t
HD, DAT
C address is
Figure 3. Timing Parameters
S6
S6
2
Figure 2. Bit Assignments
1
A P**
S5
S5
3
SUB-ADDRESS
1
2
S4
S4
4
C
REPEATED START
CONDITION
S3
S3
5
Sub-Address Byte
MSB
S2
S2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
6
t
SU, STA
S1
S1
7
6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
t
HD, STA
S0
S0
8
t
SP
5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACK
9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4
LTC3207/LTC3207-1
7
1
7
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
6
6
5
3
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
5
CONDITION
DATA BYTE
4
4
4
STOP
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
5
3
3
LSB
t
SU, STO
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
t
BUF
2
6
2
Register
CONDITION
REG10
REG11
REG12
REG13
REG14
REG15
REG0
REG1
REG2
REG3
REG4
REG5
REG6
REG7
REG8
REG9
START
1
7
1
3207 F03
8
0
0
COMMAND
Function
G/B/ENU
ULED10
ULED11
ULED12
ACK
ULED1
ULED2
ULED3
ULED4
ULED5
ULED6
ULED7
ULED8
ULED9
11
CAM
ENU
9
3207fc
STOP
3207 FO2