CAT9532WI-T1 ON Semiconductor, CAT9532WI-T1 Datasheet - Page 7

• Manufacturer Part Number: CAT9532WI-T1
• Description: IC LED DRIVER LINEAR 24-SOIC
• Manufacturer: ON Semiconductor
• Type: Linear (I²C Interface)r

Specifications of CAT9532WI-T1

• Topology: Open Drain, PWM
• Number Of Outputs: 16
• Internal Driver: Yes
• Type - Primary: Backlight, LED Blinker
• Type - Secondary: RGB
• Frequency: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 25mA
• Internal Switch(s): Yes
• Number Of Segments: 16
• Low Level Output Current: 25 mA
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Supply Current: 550 uA
• Maximum Power Dissipation: 1 W
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Efficiency: -
• Lead Free Status / Rohs Status: Details
• Other names: CAT9532WI-T1TR

FUNCTIONAL DESCRIPTION
The CAT9532 is a 16-bit I/O bus expander that
provides a programmable LED dimmer, controlled
through an I
The CAT9532 supports the I
protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master
device which generates the serial clock and all
START and STOP conditions for bus access. The
CAT9532 operates as a Slave device. Both the
Master device and Slave device can operate as either
transmitter or receiver, but the Master device controls
which mode is activated.
I
The features of the I
follows:
(1) Data transfer may be initiated only when the bus
(2) During a data transfer, the data line must remain
START and STOP Conditions
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Figure 2. Start/Stop Timing
Figure 3. CAT9532 Slave Address
© 2010 SCILLC. All rights reserved
Characteristics subject to change without notice
2
C Bus Protocol
is not busy.
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition (Figure 2).
2
C compatible serial interface.
SDA
SCL
2
C bus protocol are defined as
START CONDITION
2
C Bus data transmission
1
1
FIXED
SLAVE ADDRESS
0
0
7
PROGRAMMABLE
A2
SELECTABLE
SDA when SCL is HIGH. The CAT9532 monitors the
SDA and SCL lines and will not respond until this
condition is met.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
Device Addressing
After the bus Master sends a START condition, a
slave address byte is required to enable the CAT9532
for a read or write operation. The four most significant
bits of the slave address are fixed as binary 1100
(Figure 3). The CAT9532 uses the next three bits as
address bits.
The address bits A2, A1 and A0 are used to select
which device is accessed from maximum eight
devices on the same bus. These bits must compare to
their hardwired input pins. The 8th bit following the 7-
bit slave address is the R/W bit that specifies whether
a read or write operation is to be performed. When
this bit is set to “1”, a read operation is initiated, and
when set to “0”, a write operation is selected.
Following the START condition and the slave address
byte, the CAT9532 monitors the bus and responds
with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT9532 then performs a read or a write operation
depending on the state of the R/W bit.
HARDWARE
A1
A0
R/W
STOP CONDITION
Doc. No. MD-9001 Rev. E
CAT9532