LP5520TL/NOPB National Semiconductor, LP5520TL/NOPB Datasheet - Page 22

• Manufacturer Part Number: LP5520TL/NOPB
• Description: IC LED DRIVER RGB 25-USMD
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: RGB LED Driverr

Specifications of LP5520TL/NOPB

• Constant Current: Yes
• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 3
• Internal Driver: Yes
• Type - Primary: Backlight, Light Management Unit (LMU)
• Type - Secondary: RGB, White LED
• Frequency: 1.22kHz, 19.52kHz
• Voltage - Supply: 2.9 V ~ 5.5 V
• Voltage - Output: 5 V ~ 20 V
• Mounting Type: Surface Mount
• Package / Case: 25-MicroSMD
• Operating Temperature: -30°C ~ 85°C
• Current - Output / Channel: 60mA
• Internal Switch(s): Yes
• Efficiency: 87%
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LP5520TLTR

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Logic Inputs SS, SI/A0, SCK/SCL, IFSEL, NRST, PWMR, PWMG, PWMB and BRC
V
V
I
f
Logic input NRST
V
V
I
t
Logic Output SO
V
V
I
Logic Output SDA
V
I
SCK/SLC
I
NRST
L
IL
IH
IL
IH
OL
OH
OL
Logic Interface Characteristics
Control Interface
LP5520 supports two different interface modes:
•
•
User can define the serial interface by IF_SEL pin. IF_SEL =
0 selects the I
SPI Interface
LP5520 is compatible with SPI serial bus specification and it
operates as a slave. The transmission consists of 16-bit Write
Symbol
SPI interface (4 wire, serial)
I
2
C compatible interface (2 wire, serial)
Input Low Level
Input High Level
Logic Input Current
Clock Frequency
Input Low Level
Input High Level
Logic Input Current
Reset Pulse Width
Output Low Level
Output High Level
Output Leakage
Current
Output Low Level
2
C mode.
Parameter
I
SPI Mode
V
SPI Mode
1.65V < V
I
V
I
1.65V < V
I
V
I
1.65V < V
V
I
2
SO
SO
SO
SO
SDA
C Mode
DDIO
DDIO
DDIO
SO
= 3 mA
= 2 mA
= -3 mA
= -2 mA
= 2.8V
= 3 mA
> 1.8V
> 1.8V
> 1.8V
Conditions
DDIO
DDIO
DDIO
< 1.8V
< 1.8V
< 1.8V
SPI Write Cycle
22
and Read Cycles. One cycle consists of 7 Address bits, 1
Read/Write (RW) bit and 8 Data bits. RW bit high state defines
a Write Cycle and low defines a Read Cycle. SO output is
normally in high-impedance state and it is active only when
Data is sent out during a Read Cycle. The Address and Data
are transmitted MSB first. The Slave Select signal SS must
be low during the Cycle transmission. SS resets the interface
when high and it has to be taken high between successive
Cycles. Data is clocked in on the rising edge of the SCK clock
signal, while data is clocked out on the falling edge of SCK.
0.8 × V
V
V
DDIO
DDIO
−1.0
Min
-1.0
1.2
10
− 0.5
− 0.5
DDIO
V
V
DDIO
DDIO
Typ
0.3
0.3
0.3
− 0.3
− 0.3
0.2 × V
Max
0.5
1.0
0.4
0.5
1.0
0.5
0.5
1.0
13
5
DDIO
20186130
Units
MHz
µA
µA
µA
µs
V
V
V
V
V
V
V
V
V