A6282EESTR-T Allegro Microsystems Inc, A6282EESTR-T Datasheet - Page 10

• Manufacturer Part Number: A6282EESTR-T
• Description: IC LED DRIVER LINEAR 24-QFN
• Manufacturer: Allegro Microsystems Inc
• Type: Linear (Non-Switching)r

Specifications of A6282EESTR-T

• Constant Current: Yes
• Number Of Outputs: 16
• Internal Driver: Yes
• Type - Primary: Backlight
• Type - Secondary: Color, White LED
• Frequency: 30MHz
• Voltage - Supply: 3 V ~ 5.5 V
• Voltage - Output: 12V
• Mounting Type: Surface Mount
• Package / Case: 24-WFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 50mA
• Internal Switch(s): Yes
• Led Driver Application: LED Display, LED Signboard, Lighting
• No. Of Outputs: 16
• Output Current: 54.5mA
• Output Voltage: 12V
• Input Voltage: 3V To 5.5V
• Topology: Constant Current
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 620-1221-2

A6282
Load Supply Voltage (V
This device is designed to operate with driver voltage drops (V
of 1.0 to 3.0V. If higher voltages are dropped across the driver,
package power dissipation will increase. To minimize package
power dissipation, it is recommended to use the lowest possible
load supply voltage, V
according to the following formula:
where V
forward voltages are:
V
or for a series string of silicon diodes (approximately 0.7 V per
diode) for a group of drivers (these configurations are shown
in the figure below). If the available voltage source will cause
unacceptable power dissipation and series resistors or diodes are
undesirable, a voltage regulator can be used to provide V
Pattern Layout
To save pins and board space, the A6282 uses one pin for both
logic ground and power ground. Therefore, achieving optimal
performance requires careful attention to layout. Following the
suggestions below will improve the analog performance and logic
noise immunity.
DROP
V
V
DROP
V
V
LED
DS
F
= I
F
is the LED forward voltage. For reference, typical LED
O
× R
Typical application voltage drops
DROP
LED Type
V
Infrared
Amber
Green
Yellow
White
DROP
for a single driver, for a Zener diode (V
Blue
Red
UV
LED
V
V
DROP
V
= V
, or to set a series voltage drop, V
V
LED
DS
F
LED
LED
)
– V
F
3.5 to 4.0
3.0 to 5.5
1.8 to 2.5
2.0 to 2.5
1.9 to 3.0
1.6 to 2.5
1.2 to 1.8
3.0 to 4.0
– V
V
F
DS
(V)
V
,
V
DROP
V
V
LED
DS
F
Application Information
16-Channel Constant-Current LED Driver
LED
DROP
Z
.
),
DS
)
,
1. Place the REXT resistor as close as possible to the REXT
pin and GND pin. This will minimize parasitic inductance and
capacitance.
2. Use a separate line to the device GND pin for REXT, and sepa-
rate lines for the decoupling capacitors. The lines should join at
ground. This star grounding will improve output load regulation
and minimize any chance of oscillation.
The REXT ground line should carry only the small current from
the internal voltage reference at REXT. The high AC currents
flowing through the decoupling capacitors and their resistive and
inductive PCB lines cause noise (ground bounce) on the capacitor
ground lines. Such noise could disturb the reference voltage at
REXT and promote oscillation. Connect the exposed thermal pad
of the ES and LP packages to the power ground, along with the
decoupling capacitors, and not to the ground line for REXT.
3. Keep the output drive lines (OUT0 through OUT15) away
from the REXT pin to avoid coupling of the output signal into
the reference for the current sources. Output lines should not run
adjacent to the REXT pin or directly under the REXT pin.
4. Use decoupling capacitors on the VDD pin and the LED sup-
ply bus. Place the logic decoupling capacitor (0.1 μF, one for
each A6282) as close as possible to the VDD pin. Use at least one
10 μF capacitor from the LED supply line to device ground for at
least every two A6282s.
5. Use multilayer boards if possible.
Package Power Dissipation
The maximum allowable package power dissipation based on
package type is determined by:
where R
experimentally. Power dissipation levels based on the package are
shown in the Thermal Characteristics table.
The actual package power dissipation is determined by:
where DC is the duty cycle. The value 16 is the maximum
number of available device outputs, representing the worst-case
scenario (displaying all 16 LEDs). When the load supply voltage,
V
voltage reducer (V
DC will also reduce power dissipation. The ES and LP packages
contain an exposed thermal pad on the bottom of the package
for enhanced heat dissipation. Connect this pad to a large power
ground plane using thermal vias. JEDEC documents JESD51-3
and JESD51-5 give suggestions for PCB and thermal via designs.
LED
, is greater than 3 to 5 V, and P
JA
P
is the thermal resistance of the package, determined
D(act)
= DC × (V
DROP
P
D(max)
) must be used (figure at left). Reducing
= (150 – T
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
DS
× I
O
× 16) + (V
D(act)
A
) / R
> P
JA
D(max)
DD
,
× I
DD
, an external
) ,
10