X9530V14IT2 Intersil, X9530V14IT2 Datasheet - Page 15

• Manufacturer Part Number: X9530V14IT2
• Description: IC LASER DIODE CTRLR 14-TSSOP
• Manufacturer: Intersil
• Type: Laser Diode Controller (Fiber Optic)r

Specifications of X9530V14IT2

• Number Of Channels: 1
• Voltage - Supply: 3 V ~ 5.5 V
• Current - Supply: 9mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 14-TSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

X9530 Memory Map
The X9530 contains a 2176 bit array of mixed volatile
and nonvolatile memory. This array is split up into four
distinct parts, namely: (Refer to Figure 12.)
– General Purpose Memory (GPM)
– Look-up Table 1 (LUT1)
– Look-up Table 2 (LUT2)
– Control and Status Registers
The GPM is all nonvolatile EEPROM, located at
memory addresses 00h to 7Fh.
Figure 12. X9530 Memory Map
The Control and Status registers of the X9530 are
used in the test and setup of the device in a system.
These registers are realized as a combination of both
volatile and nonvolatile memory. These registers
reside in the memory locations 80h through 8Fh. The
reserved bits within registers 80h through 86h, must
be written as “0” if writing to them, and should be
ignored when reading. The reserved registers, from
88h through 8Fh, must not be written, and their
content should be ignored.
Both look-up tables LUT1 and LUT2 are realized as
nonvolatile EEPROM, and extend from memory
locations 90h–CFh and D0h–10Fh respectively. These
look-up tables are dedicated to storing data solely for
the purpose of setting the outputs of Current
Generators I1 and I2 respectively.
All bits in both look-up tables are preprogrammed to
“0” at the factory.
Address
10Fh
D0h
CFh
FFh
8Fh
7Fh
90h
80h
00h
7
Control & Status
General Purpose
Memory (GPM)
Look-up Table 2
Look-up Table 1
Registers
(LUT2)
(LUT1)
15
0
64 Bytes
64 Bytes
16 Bytes
128 Bytes
Size
X9530
Addressing Protocol Overview
All Serial Interface operations must begin with a
START, followed by a Slave Address Byte. The Slave
address selects the X9530, and specifies if a Read or
Write operation is to be performed.
It should be noted that the Write Enable Latch (WEL)
bit must first be set in order to perform a Write
operation to any other bit. (See “WEL: Write Enable
Latch (Volatile)” on page 7.) Also, all communication
to the X9530 over the 2-wire serial bus is conducted
by sending the MSB of each byte of data first.
Even though the 2176 bit memory consists of four
differing functions, it is physically realized as one
contiguous array, organized as 17 pages of 16 bytes
each.
The X9530 2-wire protocol provides one address byte,
therefore, only 256 bytes can be addressed directly.
The next few sections explain how to access the
different areas for reading and writing.
Figure 13. Slave Address (SA) Format
Slave Address
SA7
1
SA7 - SA4
SA3 - SA1
Bit(s)
Device Type
SA0
SA6
Identifier
0
SA5
1
SA4
Device Type Identifier
Device Address
Read or Write Operation Select
0
SA3
AS2
Description
Address
Device
SA2
AS1
AS0
SA1
Read or
November 11, 2005
Write
R/W
SA0
FN8211.1