MAX3863ETJ+ Maxim Integrated Products, MAX3863ETJ+ Datasheet - Page 3

• Manufacturer Part Number: MAX3863ETJ+
• Description: IC LASR DRVR 2.7GBPS 3.6V 32TQFN
• Manufacturer: Maxim Integrated Products
• Type: Laser Diode Driver (Fiber Optic)r

Specifications of MAX3863ETJ+

• Data Rate: 2.7Gbps
• Number Of Channels: 1
• Voltage - Supply: 3.15 V ~ 3.6 V
• Current - Supply: 58mA
• Current - Modulation: 80mA
• Current - Bias: 100mA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
otherwise noted.) (Notes 1, 9)
Note 1: Specifications at -40°C are guaranteed by design and characterization.
Note 2: Excluding I
Note 3: Guaranteed by design and characterization.
Note 4: An external capacitor at APCFILT1 and APCFILT2 is used to set the time constant.
Note 5: For both data inputs DATA+, DATA- and clock inputs CLK+, CLK-.
Note 6: Measured using a 2.7Gbps repeating 0000 0000 1111 1111 pattern.
Note 7: For pulse width, PW = 100%: Rp = Rn = 500Ω (or open) or PWC+ = PWC- ≈ +0.5V. For PW > 100%: Rp > Rn or PWC+ >
Note 8: Measured using a 2
Note 9: AC characterization performed using the circuit in Figure 1.
Note 10: Power-Supply Noise Rejection (PSNR) = 20log
Single-Ended Input (DC-Coupled)
Single-Ended Input (AC-Coupled)
Differential Input Swing
Input Data Rate
Input Return Loss
Turn-Off Delay from EN
Setup Time
Hold Time
Pulse-Width Adjustment Range
Pulse-Width Stability
Differential Pulse-Width Control
Input Range
Differential Mark Density
Differential Mark-Density Voltage
to Mark-Density Ratio
Output Edge Speed
Output Overshoot
Random Jitter
Deterministic Jitter
CC
= +3.15V to +3.6V, T
PWC-. For PW < 100%: Rp < Rn or PWC+ < PWC-.
input is applied.
PARAMETER
BIAS
_______________________________________________________________________________________
, I
A
MOD
2.7Gbps Laser Driver with Modulation
= -40°C to +85°C. Typical values are at V
13
, I
- 1 PRBS with 80 zeros + 80 ones input data pattern or equivalent.
BIASMON
SYMBOL
t
RL
R
V
t
V
V
t
HD
SU
, t
δ
ID
IS
IS
, I
IN
F
MODMON
At high
At low
At high
At low
DC-coupled
AC-coupled
NRZ (Note 3)
(Notes 3, 5)
EN = high (Note 3)
Figure 2 (Note 3)
Figure 2 (Note 3)
PWC+ and PWC- open (Notes 3, 6)
For P WC + and P W C - ( N otes 3, 7) , V
0% to 100%, V
Z
Z
(Notes 3, 6)
Data Rate = 2.7Gbps (Notes 3, 8)
Data Rate = 3.2Gbps (Notes 3, 8)
Z
L
L
L
= 25Ω (20% to 80%) (Notes 3, 6)
= 25Ω (Note 3)
= 25Ω (Notes 3, 6)
, I
FAIL
10
(V
, and I
NOISE (on VCC)
MK
CONDITIONS
PWC
+ - V
. Input clock and data are AC-coupled.
CC
MK
f ≤ 2.7GHz
2.7GHz < f ≤ 4GHz
-
= +3.3V, I
/ΔV
OUT
). V
C M
BIAS
OUT
= 0.5V
= 50mA, I
is the voltage across the 25Ω load when no
Compensation
V
C C
V
V
±185
MIN
0.05
-1.0
MOD
CC
0.4
0.2
0.2
C C
90
90
- 1.0
+
-
= 40mA, T
±220
TYP
15.5
V
3.2
0.8
17
14
50
±7
10
CC
8
A
V
C C
V
= +25°C, unless
±18.5
±0.85
V
MAX
0.05
CC
0.4
2.0
1.6
1.0
1.0
1.3
C C
85
40
40
- 0.1
+
-
UNITS
ps
Gbps
ps
V
V/%
dB
µs
ps
ps
ps
ps
ps
%
P-P
V
V
V
V
RMS
P-P
3