MAX5952CEAX+ Maxim Integrated Products, MAX5952CEAX+ Datasheet - Page 17
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MAX5952CEAX+
Manufacturer Part Number
MAX5952CEAX+
Description
IC PSE CNTRLR FOR POE 36-SSOP
Manufacturer
Maxim Integrated Products
Type
Power Over Ethernet Controller (PoE)r
Datasheet
1.MAX5952AUAX.pdf
(50 pages)
Specifications of MAX5952CEAX+
Applications
Remote Peripherals (Industrial Controls, Cameras, Data Access)
Internal Switch(s)
No
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
36-BSOP (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
A valid PD has a 25kΩ discovery signature characteristic
as specified in the IEEE 802.3af/at standard. Table 1
shows the IEEE 802.3af/at specification for a PSE detect-
ing a valid PD signature. See the Typical Operating
Circuits and Figure 1 (Detection, Classification, and
Power-Up Port Sequence). The MAX5952 can probe and
categorize different types of devices connected to the
port such as: a valid PD, an open circuit, a low resistive
load, a high resistive load, a high capacitive load, a posi-
tive DC supply, or a negative DC supply.
During detection, the MAX5952 keeps the external
MOSFET off and forces two probe voltages through the
DET_ input. The current through the DET_ input is mea-
sured as well as the voltage at OUT_. A two-point slope
measurement is used as specified by the IEEE 802.3af
standard to verify the device connected to the port. The
MAX5952 implements appropriate settling times and a
100ms digital integration to reject 50Hz/60Hz power-
line noise coupling.
Table 1. PSE PI Detection Modes Electrical Requirement
(Table 33-2 of the IEEE 802.3af Standard)
Open-Circuit Voltage
Short-Circuit Current
Valid Test Voltage
Voltage Difference
Between Test Points
Time Between Any Two
Test Points
Slew Rate
Accept Signature
Resistance
Reject Signature
Resistance
Open-Circuit Resistance
Accept Signature
Capacitance
Reject Signature
Capacitance
Signature Offset Voltage
Tolerance
Signature Offset Current
Tolerance
PARAMETER
______________________________________________________________________________________
SYMBOL
R
C
V
∆V
V
R
C
R
V
GOOD
VALID
GOOD
V
SLEW
OPEN
I
t
I
BAD
BAD
SC
BP
OS
OC
TEST
OS
High-Power, Quad, PSE Controller
< 15
MIN
500
2.8
19
10
—
—
—
1
2
0
0
MAX
26.5
> 33
150
0.1
2.0
30
10
12
—
—
—
—
5
for Power-Over-Ethernet
An external diode, in series with the DET_ input,
restricts PD detection to the first quadrant as specified
by the IEEE 802.3af/at standard. To prevent damage to
non-PD devices, and to protect itself from an output
short circuit, the MAX5952 limits the current into DET_
to less than 2mA maximum during PD detection.
In midspan mode, the MAX5952 waits 2.2s before
attempting another detection cycle after every failed
detection. The first detection, however, happens imme-
diately after issuing the detection command.
The CLC_EN bit in register R23h[5] enables the large
capacitor detection feature for legacy PD devices.
When CLC_EN = 1, the high-capacitance detection limit
is extended up to 100µF. CLC_EN = 0 is the default
condition for the normal capacitor size detection. See
Table 1 and the Register Map and Description section.
UNITS
V/µs
mA
ms
kΩ
kΩ
kΩ
nF
µF
µA
V
V
V
V
In detection mode only
In detection mode only
This timing implies a 500Hz maximum probing
frequency
ADDITIONAL INFORMATION
High-Capacitance Detection
17