MIC2593-2BTQ Micrel Inc, MIC2593-2BTQ Datasheet - Page 5
![IC CTRLR HOTPLUG PCI DUAL 48TQFP](/photos/6/84/68454/576-48-tqfp_sml.jpg)
MIC2593-2BTQ
Manufacturer Part Number
MIC2593-2BTQ
Description
IC CTRLR HOTPLUG PCI DUAL 48TQFP
Manufacturer
Micrel Inc
Type
Hot-Swap Controllerr
Datasheet
1.MIC2593-2YTQ.pdf
(26 pages)
Specifications of MIC2593-2BTQ
Applications
PCI, PCI-X
Internal Switch(s)
No
Voltage - Supply
3.3V, 5V, ±12V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Micrel, Inc.
September 2008
Pin Number
15, 22
44, 43
45, 42
40, 41
33, 46
2, 35
1, 36
4, 38
48
47
37
CFILTERA, CFILTERB
AUXENA, AUXENB
/FAULTA, /FAULTB
VAUXA, VAUXB
GPIA, GPIB
ONA, ONB
Pin Name
A1, A0
GND
SDA
SCL
/INT
Pin Function
3.3VAUX[A/B] Output to PCI Card Slot: These outputs connect the 3.3AUX pin
of the PCI connectors to VSTBY[A/B] via internal 400mΩ MOSFETs. These
outputs are current limited and protected against short-circuit faults.
Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA and
MAINB (5V, 3.3V, +12V and –12V) outputs. Taking ON[A/B] low after a fault
resets the 5V, 3.3V, +12V and/or –12V fault latches for the affected slot. Tie
these pins to GND if using SMI power control. Also, see pin description for
/FAULTA and /FAULTB.
Enable Inputs: Rising-edge triggered. Used to enable or disable VAUXA and
VAUXB outputs. Taking AUXEN[A/B] low after a fault resets the respective slot’s
Aux Output Fault Latch. Tie these pins to GND if using SMI power control. Also,
see pin description for /FAULTA and /FAULTB.
Overcurrent Timer (Filter) Capacitor [A/B]: Capacitors connected between these
pins and GND set the duration of t
remains in current limit before its circuit breaker is tripped.
/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the circuit
breaker trips due to a fault condition (overcurrent, input undervoltage,
overtemperature). Each pin requires an external pull-up resistor to VSTBY.
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B] was
asserted in response to a fault condition on one of the slot’s MAIN outputs (5V,
3.3V, +12V, or –12V).
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if /FAULT[A/B]
was asserted in response to a fault condition on the slot’s VAUX output. If a fault
condition occurred on both the MAIN and VAUX[A/B] outputs of the same slot,
then both ON[A/B] and AUXEN[A/B] must be brought low to de-assert the
/FAULT[A/B] output.
General Purpose Inputs: The states of these two inputs are available by reading
the Common Status Register, Bits [4:5]. If not used, connect each pin to GND.
SMBus Address Select Pins: Connect to ground or leave open in order to 41 A0
program device SMBus base address. These inputs have internal pull-up
resistors to VSTBY[A/B].
SMBus Data: Bidirectional SMBus data line.
SMBus Clock: Input.
Interrupt Output: Open-drain, active-low. Asserted whenever a power fault is
detected if the INTMSK bit (CS Register Bit D[3]) is a logical "0". This output is
de-asserted by performing an "echo reset" to the appropriate fault bit(s) in the
STAT[A/B] and/or CS registers. This pin requires an external pull-up resistor to
V
IC Ground Connections: Tie directly to the system’s analog ground plane
directly at the device.
STBY
.
5
FLT
. t
FLT
is the amount of time for which a slot
M9999-092208
MIC2593