ISL6115CBZA Intersil, ISL6115CBZA Datasheet - Page 3
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ISL6115CBZA
Manufacturer Part Number
ISL6115CBZA
Description
IC CTRLR POWER DISTRIB 8-SOIC
Manufacturer
Intersil
Type
Hot-Swap Controllerr
Datasheet
1.ISL6117CBZA.pdf
(13 pages)
Specifications of ISL6115CBZA
Applications
General Purpose
Internal Switch(s)
No
Voltage - Supply
10.2 V ~ 13.8 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Output Voltage
6V
Internal Switch
No
Supply Voltage Range
10.2V To 13.8V
Digital Ic Case Style
SOIC
No. Of Pins
8
Operating Temperature Range
0°C To +85°C
Termination Type
SMD
Rohs Compliant
Yes
Filter Terminals
SMD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL6115CBZA
Manufacturer:
INTERSIL
Quantity:
20 000
Company:
Part Number:
ISL6115CBZA-T
Manufacturer:
LT
Quantity:
2 500
Part Number:
ISL6115CBZA-T
Manufacturer:
INTERSIL
Quantity:
20 000
Pin Descriptions
PIN # SYMBOL
1
2
3
4
5
6
7
8
PGOOD
PWRON
GATE
ISEN
CTIM
ISET
VDD
VSS
Current Set
Current Sense
External FET Gate
Drive Pin
Chip Return
Chip Supply
Current Limit Timing
Capacitor
Power Good Indicator Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open
Power-ON
FUNCTION
3
ISL6115, ISL6116, ISL6117, ISL6120
Connect to the low side of the current sense resistor through the current limiting set resistor.
This pin functions as the current limit programming pin.
Connect to the more positive end of sense resistor to measure the voltage drop across this
resistor.
Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to
ground sets the turn-on ramp. At turn-on this capacitor will be charged to V
(ISL6115) and to V
12V chip supply. This can be either connected directly to the +12V rail supplying the
switched load voltage or to a dedicated V
Connect a capacitor from this pin to ground. This capacitor determines the time delay
between an overcurrent event and chip output shutdown (current limit time-out). The
duration of current limit time-out is equal to 93kΩ x C
drain N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than
the UV level for the particular IC.
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is
driven high to a maximum of 5V or is left open. Do not drive this input >5V. After a
current limit time-out, the chip is reset by a low level signal applied to this pin. This input
has 20µA pull-up capability.
DD
(ISL6116, ISL6117, ISL6120) by a 10µA current source.
DESCRIPTION
SS
+12V supply.
TIM
.
April 29, 2010
DD
FN9100.7
+5V