ISL6115CBZA-T Intersil, ISL6115CBZA-T Datasheet - Page 11

• Manufacturer Part Number: ISL6115CBZA-T
• Description: IC CTRLR POWER DISTRIB 8-SOIC
• Manufacturer: Intersil
• Type: Hot-Swap Controllerr

Specifications of ISL6115CBZA-T

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 10.2 V ~ 13.8 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ISL6115EVAL1Z Board
The ISL6115EVAL1Z is default provided as a +12V high
side switch controller with the CR level set at ~1.5A.
See Figure 21 for ISL6115EVAL1Z schematic and Table
4 for BOM. Bias and load connection points are
provided along with test points for each IC pin.
With J1 installed the ISL6115 will be biased from the
+12V supply (V
VLOAD+. PWRON pin pulls high internally enabling the
ISL6115 if not driven low via PWRON test point or J2.
With R
the 10mΩ sense resistor (R
a nominal CR level of 1.5A. The 0.01µF delay time to
latch-off capacitor results in a nominal 1ms before
latch-off of output after an OC event.
Also included with the ISL6115EVAL1Z board are one
each of the ISL6116, ISL6117 and ISL6120 for
evaluation of those ICs in a high side application.
Remove J1 and provide a separate +12V IC bias supply
via V
Reconfiguring the ISL6115EVAL1Z board for a higher
CR level can be done by changing the R
R
much higher current.
ISL6116EVAL1 Board
The ISL6116EVAL1 is default configured as a negative
voltage low side switch controller with a ~2.4A CR
level. See Figure 22 for ISL6116EVAL1 schematic and
Table 4 for BOM and component description. This basic
configuration is capable of controlling both larger
positive or negative potential voltages with minimal
changes.
FIGURE 21. ISL6115EVAL1Z HIGH SIDE SWITCH
ISET
R1
U1
BIAS
resistor values as the provided FET is rated for a
3
VIN
VOUT
= 750Ω the CR Vth is set to 15mV and with
test point.
R3
C1
R2
APPLICATION
IN
1
2
3
4
J1
) being switched. Connect the load to
VLOAD+
ISL6115
U2
C2
11
V
1
+12V
BIAS
) the ISL6115EVAL1Z has
ISL6115, ISL6116, ISL6117, ISL6120
8
7
6
5
AGND
V
BIAS
R4
SENSE
PGOOD
J2
PWRON
C3
C
TIM
and/or
J1
FIGURE 22. ISL6116EVAL1 NEGATIVE VOLTAGE LOW
+VBUS
HI J2
Bias and load connection points are provided in
addition to test points, TP1 to TP8 for each IC pin. The
terminals, J1 and J4 are for the bus voltage and return,
respectively, with the more negative potential being
connected to J4. With the load between terminals J2
and J3 the board is now configured for evaluation. The
device is enabled through LOGIN, TP9 with a TTL
signal. ISL6116EVAL1 includes a level shifting circuit
with an opto-coupling device for the PWRON input so
that standard TTL logic can be translated to the -V
reference for chip control.
When controlling a positive voltage, PWRON can be
accessed at TP8.
The ISL6116EVAL1 is provided with a high voltage
linear regulator for convenience to provide chip bias
from ±24V to ±350V. This can be removed and
replaced with the zener and resistor bias scheme as
discussed earlier. High voltage regulators and power
discrete devices are no longer available from Intersil
but can be purchased from other semiconductor
manufacturers.
Reconfiguring the ISL6116EVAL1 board for a higher CR
level can be done by changing the R
resistor values as the provided FET is 75A rated. If
evaluation at >60V, an alternate FET must be chosen
with an adequate BV
G
R
1
R11
R6
LOAD
C1
SIDE CONTROLLER
C3
D2
J3 LO
R7
Q2
DD1
3.3V
ISL6116
DSS
U1
R5
R1
R2
.
R9
PWRON
R8
J4
-VBUS
TP8
SENSE
OT1
and R
LOGIN
TP9
R10
April 29, 2010
ON
OFF
0V to
FN9100.7
ISET
5V