LTC4219IDHC-12#PBF Linear Technology, LTC4219IDHC-12#PBF Datasheet - Page 14

• Manufacturer Part Number: LTC4219IDHC-12#PBF
• Description: IC CONTROLLER HOT SWAP12A 16DFN
• Manufacturer: Linear Technology
• Type: Hot-Swap Switchr

Specifications of LTC4219IDHC-12#PBF

• Applications: General Purpose
• Internal Switch(s): Yes
• Current Limit: 5.6A
• Voltage - Supply: 2.9 V ~ 15 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-WFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
LTC4219
Power Good Indication
In addition to setting the foldback current limit threshold,
the FB pin is used to determine a power good condition.
The LTC4219-12 and LTC4219-5 use an internal resis-
tive divider on the OUT pin to drive the FB pin. On the
LTC4219-12, the PG comparator indicates logic high when
OUT pin rises above 10.5V. If the OUT pin subsequently falls
below 10.3V, the comparator toggles low. On the LTC4219-
5 the PG comparator drives high when the OUT pin rises
above 4.35V and low when OUT falls below 4.27V.
Once the PG comparator is high, the GATE pin voltage is
monitored with respect to the OUT pin. Once the GATE
minus OUT voltage exceeds 4.2V, the PG pin goes low.
This indicates to the system that it is safe to load the OUT
pin while the MOSFET is completely turned “on”. The PG
pin goes high when the GATE is commanded off (using
the EN1, EN2 or SENSE pins) or when the PG comparator
drives low.
Design Example
Consider the following design example (Figure 5): V
12V, I
= 10.5V.
14
MAX
= 5A. I
INRUSH
12V
= 100mA, C
L
= 330μF, V
Figure 5. 5A, 12V Card Resident Application
12V
R3
10k
C1
0.1μF
PWRGD
V
EN1
EN2
FLT
TIMER
INTV
DD
IN
LTC4219DHC-12
CC
=
GND
The inrush current is defi ned by the current required to
charge the output capacitor using the fi xed 0.3V/ms GATE
charge up rate. The inrush current is defi ned as:
As mentioned previously, the charge up time is the out-
put voltage (12V) divided by the output rate of 0.3V/ms
resulting in 40ms. The peak power dissipation of 12V at
100mA (or 1.2W) is within the SOA of the pass MOSFET for
40ms (see MOSFET SOA curve in the Typical Performance
Characteristics section).
Next the power dissipated in the MOSFET during overcurrent
must be limited. The active current limit uses a timer to
prevent excessive energy dissipation in the MOSFET. The
worst-case power dissipation occurs when the voltage
versus current profi le of the foldback current limit is at the
maximum. This occurs when the current is 6.1A and the
voltage is one half of the 12V or 6V. See the Current Limit
Sense Voltage vs FB Voltage in the Typical Performance
Characteristics section to view this profi le. In order to
survive 36W, the MOSFET SOA dictates a maximum time
of 10ms (see SOA graph). Use the internal 2ms timer
invoked by tying the TIMER pin to INTV
I
I
OUT
MON
INRUSH
PG
12V
= C
R1
10k
R2
20k
+
L
•
C
330μF
⎛
⎝ ⎜
L
0.3V
ms
V
12V
5A
ADC
OUT
⎞
⎠ ⎟
4219 F05
= 330µF •
⎛
⎝ ⎜
0.3V
ms
CC
.
⎞
⎠ ⎟
= 100mA
4219fb