LTC4253ACGN#PBF Linear Technology, LTC4253ACGN#PBF Datasheet - Page 8

• Manufacturer Part Number: LTC4253ACGN#PBF
• Description: IC HOT SWAP CONTRLR -48V 16-SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4253ACGN#PBF

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 8.2 V ~ 14.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC4253/LTC4253A
Typical perForMance characTerisTics
pin FuncTions
EN2 (Pin 1): Power Good Status Output Two Enable. This
is a TTL compatible input that is used to control PWRGD2
and PWRGD3 outputs. When EN2 is driven low, both
PWRGD2 and PWRGD3 will go high. When EN2 is driven
high, PWRGD2 will go low provided PWRGD1 has been
active for more than one power good sequence delay
(t
to control the power good sequence. This pin is internally
pulled low by a 120µA current source.
PWRGD2 (Pin 2): Power Good Status Output Two. Power
good sequence starts with PWRGD1 latching active low.
PWRGD2 will latch active low after EN2 goes high and
after one power good sequence delay t
the sequencing timer from the time PWRGD1 goes low,
whichever comes later. PWRGD2 is reset by PWRGD1
going high or EN2 going low. This pin is internally pulled
high by a 50µA current source.
PWRGD1 (Pin 3): Power Good Status Output One. At start-
up, PWRGD1 latches active low and starts the power good
sequence when the DRAIN pin is below 2.39V and GATE
is within 2.8V of V
(UVLO), RESET going high or circuit breaker fault time-out.
This pin is internally pulled high by a 50µA current source.
8
SQT
60
58
56
54
52
50
48
46
44
42
40
) provided by the sequencing timer. EN2 can be used
–55 –35 –15
I
I
V
PGH
IN
PWRGD
= 2mA
vs Temperature
= 0V
TEMPERATURE (°C)
5
IN
25
. PWRGD1 status is reset by UV, V
45
65
85 105 125
4253 G28
SQT
300
290
280
270
260
250
240
230
220
210
200
provided by
–55 –35 –15
t
SS
I
SS PIN FLOATING
V
IN
SS
= 2mA
vs Temperature
RAMPS FROM 0.2V TO 2V
TEMPERATURE (°C)
IN
5
25
V
positive side of the supply through a dropping resistor. A
shunt regulator clamps V
undervoltage lockout (UVLO) circuit holds GATE low until
the V
UV is high, OV is low and V
starts an initial timing cycle before initiating GATE ramp
up. If V
LTC4253A), GATE pulls low immediately.
RESET (Pin 5): Circuit Breaker Reset Pin. This is an asyn-
chronous TTL compatible input. RESET going high will pull
GATE, SS, TIMER, SQTIMER low and the PWRGD outputs
high. The RESET pulse must be wide enough to discharge
any voltage on the TIMER pin below V
of a latched fault, the chip waits for the interlock conditions
before recovering as described in Interlock Conditions in
the Operation section.
SS (Pin 6): Soft-Start Pin. This pin is used to ramp inrush
current during start up, thereby effecting control over di/dt.
A 20X attenuated version of the SS pin voltage is presented
to the current limit amplifier. This attenuated voltage limits
the MOSFET’s drain current through the sense resistor
during the soft-start current limiting. At the beginning of
IN
45
(Pin 4): Positive Supply Input. Connect this pin to the
65
IN
IN
pin is greater than V
85 105 125
drops below approximately 8.2V (8.5V for the
4253 G29
500
450
400
350
300
250
200
150
100
50
0
–55 –35 –15
IN
t
SQ
I
V
IN
IN
SQTMR
at 13V above V
LKO
= 2mA
vs Temperature
comes out of UVLO, TIMER
, overriding UV and OV. If
RAMPS FROM 0.5V TO 3.5V
TEMPERATURE (°C)
5
TMRL
25
45
. After the reset
EE
65
. An internal
85 105 125
425353afd
4253 G30