LTC4252A-2IMS Linear Technology, LTC4252A-2IMS Datasheet - Page 23

• Manufacturer Part Number: LTC4252A-2IMS
• Description: IC CTRLR HOTSWAP NEG VOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4252A-2IMS

• Applications: General Purpose
• Internal Switch(s): No
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Family Name: LTC4252A-2
• Package Type: MSOP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 0.86mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS INFORMATION
satisfied before a GATE start-up cycle begins. SS ramps up
as dictated by R
current limit amplifier until SS crosses 20 • V
releasing GATE, 58μA sources into the external MOSFET
gate and compensation network. When the GATE voltage
reaches the MOSFET’s threshold, current begins flowing
into the load capacitor at time point 5. At time point 6,
load current reaches the SS control level and the analog
current limit loop activates. Between time points 6 and 8,
the GATE voltage is servoed, the SENSE voltage is regulated
at V
current. If the SENSE voltage (V
ACL
(–48RTN) – (–48V)
(t) and soft-start limits the slew rate of the load
GND – V
PWRGD
SENSE
TIMER
DRAIN
UV/OV
EE
GATE
V
OUT
V
OR
SS
SS
IN
• C
1
Figure 10. Power-Up Timing with a Short Pin (All Waveforms Are Referenced to V
SS
V
; GATE is held low by the analog
GATEL
V
UVHI
V
LKO
UV CLEARS V
2
SENSE
UVHI
– V
5.8μA
, CHECK OV < V
INITIAL TIMING
EE
) reaches the
OS
. Upon
OVHI
V
ACL
TMRH
, GATE < V
CB
OS
V
+ V
+ V
TMRL
OS
OS
)
)
58μA
GATEL
3 4 56
V
activates. The TIMER capacitor, C
+ 8 • I
charge, load current begins to decline. At point 8, the load
current falls and the SENSE voltage drops below V
The analog current limit loop shuts off and the GATE pin
ramps further. At time point 9, the SENSE voltage drops
below V
5.8μA discharge cycle (cool off). When GATE ramps past
V
time point 11, GATE reaches its maximum voltage as
determined by V
TIMER CLEARS V
CB
GATEH
, SENSE < V
START-UP
threshold at time point 7, the circuit breaker TIMER
DRN
LTC4252A-1/LTC4252A-2
GATE
7
58μA
threshold at time point 10, PWRGD pulls low. At
CB
8 9
) current pull-up. As the load capacitor nears full
CB
DRN
and the fault TIMER cycle ends, followed by a
TMRL
1011
LTC4252-1/LTC4252-2
, CHECK GATE < V
V
V
V
V
V
IN
ACL
CB
DRNCL
DRNL
IN
– V
.
GATEH
OS
5.8μA
AND TIMER < V
GATEL
, SENSE < V
TMRL
EE
T
, is charged by a (230μA
)
5.8μA
CB
425212 F10
OS
23
ACL
425212fc
(t).