LTC4252A-2CMS#PBF Linear Technology, LTC4252A-2CMS#PBF Datasheet - Page 17

• Manufacturer Part Number: LTC4252A-2CMS#PBF
• Description: IC CNTRLR HOTSWAP NEGVOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4252A-2CMS#PBF

• Applications: General Purpose
• Internal Switch(s): No
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
2.5% or more will eventually trip the circuit breaker and
shut down the LTC4252. Figure 5 shows the circuit breaker
response time in seconds normalized to 1μF for I
0μA. The asymmetric charging and discharging of C
a fair gauge of MOSFET heating.
The normalized circuit response time is estimated by
SHUTDOWN COOLING CYCLE
For the LTC4252-1 (latchoff version), TIMER latches high
with a 5.8μA pull-up after the circuit breaker fault TIMER
reaches 4V. For the LTC4252-2 (automatic retry version),
a shutdown cooling cycle begins if TIMER reaches the
4V threshold. TIMER starts with a 5.8μA pull-down until
it reaches the 1V threshold. Then, the 5.8μA pull-up turns
back on until TIMER reaches the 4V threshold. Four 5.8μA
pull-down cycles and three 5.8μA pull-up cycles occur
between the 1V and 4V thresholds, creating a time interval
given by:
At the 1V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
C
t
SHUTDOWN
T
(μF)
t
Figure 5. Circuit-Breaker Response Time
=
0.01
0.1
10
⎡ ⎣
1
(
235.8+8 •I
=
0
7 • 3V •C
5.8μA
C
T
20
(μF)
t
FAULT DUTY CYCLE (%)
=
T
4
DRN
40
)
•D–5.8
60
4
DRN
I
DRN
80
⎤ ⎦
= 0μA
425212 F05
100
DRN
T
(4)
(5)
is
=
SOFT-START
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFET’s SOA rating if powering up into an active load.
If SS floats, an internal current source ramps SS from 0V
to 2.2V for the LTC4252 or 0V to 1.4V for the LTC4252A
in about 230μs. Connecting an external capacitor C
from SS to ground modifies the ramp to approximate an
RC response of:
An internal resistive divider (95k/5k for the LTC4252 or
47.5k/2.5k for the LTC4252A) scales V
times to give the analog current limit threshold:
This allows the inrush current to be limited to V
The offset voltage, V
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
GATE
GATE is pulled low to V
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out. When GATE turns
on, a 58μA current source charges the MOSFET gate and
any associated external capacitance. V
drive to no more than 14.5V.
Gate-drain capacitance (C
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at V
V
V
SS
ACL
LTC4252A-1/LTC4252A-2
(t)≈V
(t)=
SS
LTC4252-1/LTC4252-2
V
SS
20
• 1–e
⎛
⎜
⎜
⎜
⎝
(t)
–V
OS
⎛
⎜
⎝
OS
–
(10mV), ensures C
R SS • C SS
EE
GD
t
under any of the following
) feedthrough at the first
⎞
⎟
⎠
⎞
⎟
⎟
⎟
⎠
SS
IN
SS
(t) down by 20
limits the gate
is sufficiently
ACL
17
(t)/R
425212fc
(6)
(7)
SS
IN
S
.