LTC4300A-2CMS8#TR Linear Technology, LTC4300A-2CMS8#TR Datasheet - Page 8

• Manufacturer Part Number: LTC4300A-2CMS8#TR
• Description: IC BUFFER BUS 2WR HOTSWAP 8-MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Switchr

Specifications of LTC4300A-2CMS8#TR

• Applications: General Purpose, Buffer/Bus Extender
• Internal Switch(s): Yes
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

OPERATIO
LTC4300A-1/LTC4300A-2
Start-Up
When the LTC4300A first receives power on its V
either during power-up or during live insertion, it starts in
an undervoltage lockout (UVLO) state, ignoring any activ-
ity on the SDA and SCL pins until V
the LTC4300A-2, the part also waits for V
2V. This ensures that the part does not try to function until
it has enough voltage to do so.
During this time, the 1V precharge circuitry is also active
and forces 1V through 100k nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged into
a live backplane, the voltage on the backplane SDA and SCL
busses may be anywhere between 0V and V
the SCL and SDA pins to 1V minimizes the worst-case
voltage differential these pins will see at the moment of con-
nection, therefore minimizing the amount of disturbance
caused by the I/O card.
Once the LTC4300A comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the backplane side to indicate
the completion of a data transaction. When either one
occurs, the part also verifies that both the SDAOUT and
SCLOUT voltages are high. When all of these conditions
are met, the input-to-output connection circuitry is acti-
vated, joining the SDA and SCL busses on the I/O card with
those on the backplane, and the rise time accelerators are
enabled.
Connection Circuitry
Once the connection circuitry is activated, the functional-
ity of the SDAIN and SDAOUT pins is identical. A low forced
on either pin at any time results in both pin voltages being
low. For proper operation, logic low input voltages should
be no higher than 0.4V with respect to the ground pin voltage
of the LTC4300A. SDAIN and SDAOUT enter a logic high
state only when all devices on both SDAIN and SDAOUT
release high. The same is true for SCLIN and SCLOUT. This
important feature ensures that clock stretching, clock syn-
chronization, arbitration and the acknowledge protocol al-
ways work, regardless of how the devices in the system are
tied to the LTC4300A.
8
U
CC
rises above 2.5V. For
CC2
CC
. Precharging
to rise above
CC
pin,
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms, as
described here.
Input to Output Offset Voltage
When a logic low voltage, V
LTC4300A’s data or clock pins, the LTC4300A regulates
the voltage on the other side of the chip (call it V
a slightly higher voltage, as directed by the following
equation:
where R is the bus pull-up resistance in ohms. For ex-
ample, if a device is forcing SDAOUT to 10mV where
V
the voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 100
= 118mV. See the Typical Performance Characteristics
section for curves showing the offset voltage as a function
of V
Propagation Delays
During a rising edge, the rise-time on each side is deter-
mined by the combined pull-up current of the LTC4300A
boost current and the bus resistor and the equivalent
capacitance on the line. If the pull-up currents are the
same, a difference in rise-time occurs which is directly
proportional to the difference in capacitance between the
two sides. This effect is displayed in Figure 1 for V
and a 10k pull-up resistor on each side (50pF on one side
and 150pF on the other). Since the output side has less
capacitance than the input, it rises faster and the effective
t
There is a finite propagation delay, t
connection circuitry for falling waveforms. Figure 2 shows
the falling edge waveforms for the same V
resistors and equivalent capacitance conditions as used in
Figure 1. An external NMOS device pulls down the voltage
on the side with 150pF capacitance; the LTC4300A pulls
down the voltage on the opposite side, with a delay of
55ns. This delay is always positive and is a function of
PLH
CC
V
= 3.3V and the pull-up resistor R on SDAIN is 10k, then
CC
LOW2
is negative.
and R.
= V
LOW1
+ 75mV + (V
LOW1
CC
, is driven on any of the
/R) • 100
PHL
, through the
sn4300a12 4300a12fs
CC
CC
, pull-up
LOW2
= 3.3V
) to