LTC1647-3CGN#PBF Linear Technology, LTC1647-3CGN#PBF Datasheet - Page 12

• Manufacturer Part Number: LTC1647-3CGN#PBF
• Description: IC CTLR HOTSWAP DUAL 16-SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC1647-3CGN#PBF

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 2.7 V ~ 16.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Linear Misc Type: Positive Low Voltage
• Family Name: LTC1647-3
• Package Type: SSOP N
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 16.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC1647-1/
LTC1647-2/LTC1647-3
APPLICATIONS INFORMATION
an input supply greater than 10V at V
Zener is recommended between the corresponding GATE1
or GATE2 pin and GND as shown in Figures 1 and 4.
The R
make V
+ V
This restricts the choice of MOSFETs to very low R
At higher V
relaxed. MOSFET package dissipation (P
restrict the value of R
Power Supply Ramping
V
path (Figure 1). R1 provides load current fault detection
and R2 prevents MOSFET high frequency oscillation. By
ramping the gate of the pass transistor at a controlled
rate (dV/dt = 10μA/C1), the transient surge current
(I = C
backplane is limited to a safe value when the board is
inserted into the connector.
When power is first applied to V
A low-to-high transition at the ON pin initiates GATE ramp-
up. The rising dV/dt of GATE is set by 10μA/C1 (Figure 5),
where C1 is the total external capacitance between
GATE and GND. The ramp-up time for V
t = (V
A high-to-low transition at the ON pin initiates a GATE
ramp-down at a slope of – 50μA/C1. This rate is usually
adequate as the supply bypass capacitors take time to
discharge through the load.
12
V
OUT
CC
CB
+ Δ V
LOAD
CC
DS(ON)
is controlled by placing MOSFET Q1 in the power
= 0.1V yields 3% error at maximum load current.
GATE
DS
V
V
•C1)/10μA.
0V
0V
CC
CC
•dV/dt = 10μA•C
a small percentage of V
CC
Figure 5. Supply Turn-On/Off with ON
of the external pass transistor must be low to
voltages, the R
DS(ON)
LOAD
V
.
RAMP-UP
SLOPE = 10μA/C1
ON
DS(ON)
/C1) drawn from the main
CC
SLOPE = –50μA/C1
V
C
OUT
LOAD
, the GATE pin pulls low.
V
CC
GATE
RAMP-DOWN
DISCHARGES
. At V
requirement can be
CC1
OUT
D
or V
CC
and T
= 3.3V, V
is equal to
CC2
, a 24V
DS(ON)
J
1647-1/2/3 F05
) may
DS
.
If the ON pin is connected to V
V
the undervoltage lockout threshold, V
the threshold is exceeded, GATE ramps at a controlled rate
of 10μA/C1. When the power supply is disconnected, the
body diode of Q1 holds V
The GATE voltage droops at a rate determined by V
V
and GATE pulls down to GND.
V
CC
CC
CC
+ Δ V
(5V LOGIC)
is first applied, GATE is held low until V
drops below V
GATE
FAULT
V
V
V
0V
0V
CC
CC
CC
V
ON
0.1μF
CC
– V
C3
V
V
SENSE
Figure 6. Supply Turn-On/Off with V
FAULT
GATE
OUT OF UVLO
V
LKO
R3
15k
Figure 7. Autoretry Sequence
LKO
2
4
C
UNPLUGGED
ON/FAULT
GND
LOAD
– V
V
CC
1
DISCHARGES
LKH
RAMP-UP
SLOPE = 10μA/C1
0.01Ω
CC
V
R1
V
V
CC
CC
GATE
, the LTC1647 enters UVLO
SENSE
about 700mV below V
CC
V
OUT
, or is pulled high before
8
LTC1647-2
IRF7413
t
RESET
LKO
GATE
Q1
6
t
V
DUE TO V
t
RAMP
R2
10Ω
DELAY
GATE
(Figure 6). Once
INTO UVLO
V
CC
LKO
CC
1647-1/2/3 F07
FAST RAMP-DOWN
AT UNDERVOLTAGE
LOCKOUT
+
DROOP
– V
rises above
CC
LKH
C1
10nF
C
LOAD
1647-1/2/3 F06
V
OUT
CC
1647fa
OUT
. If
.