MAX5952AUAX+ Maxim Integrated Products, MAX5952AUAX+ Datasheet - Page 23

• Manufacturer Part Number: MAX5952AUAX+
• Description: IC PSE CNTRLR FOR POE 36-SSOP
• Manufacturer: Maxim Integrated Products
• Type: Power Over Ethernet Controller (PoE)r

Specifications of MAX5952AUAX+

• Applications: Remote Peripherals (Industrial Controls, Cameras, Data Access)
• Internal Switch(s): No
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-BSOP (0.300", 7.5mm Width)
• Product: PoE / LAN Solutions
• Supply Voltage (max): 60 V
• Supply Voltage (min): 32 V
• Power Dissipation: 941 mW
• Operating Temperature Range: 0 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Each transmission consists of a START condition (Figure
6) sent by a master, followed by the MAX5952 7-bit
slave address plus R/W bit, a register address byte, one
or more data bytes, and finally a STOP condition.
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master fin-
ishes communicating with the slave, the master issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The STOP condition frees the
bus for another transmission.
Figure 6. START and STOP Conditions
Figure 8. Acknowledge
SDAIN
SDA/
SCL
START
BY TRANSMITTER
S
BY RECEIVER
SDA
SDA
SCL
______________________________________________________________________________________
START CONDITION
START and STOP Conditions
S
High-Power, Quad, PSE Controller
Serial Addressing
1
STOP
P
2
for Power-Over-Ethernet
Each clock pulse transfers one data bit (Figure 7). The
data on SDA must remain stable while SCL is high.
The acknowledge bit is a clocked 9th bit (Figure 8) that
the recipient uses to handshake receipt of each byte of
data. Thus each byte effectively transferred requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA (or the SDAOUT in the 3-wire
interface) during the acknowledge clock pulse, so that
the SDA line is stable low during the high period of the
clock pulse. When the master transmits to the MAX5952,
the MAX5952 generates the acknowledge bit. When the
MAX5952 transmits to the master, the master generates
the acknowledge bit.
Figure 7. Bit Transfer
SDA
SCL
CLOCK PULSE FOR ACKNOWLEDGEMENT
DATA LINE STABLE;
DATA VALID
8
DATA ALLOWED
CHANGE OF
9
Acknowledge
Bit Transfer
23
.