ADE7758ARW Analog Devices Inc, ADE7758ARW Datasheet - Page 64

• Manufacturer Part Number: ADE7758ARW
• Description: IC ENERGY METERING 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7758ARW

• Rohs Status: RoHS non-compliant
• Input Impedance: 380 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 8mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• Lead Free Status / RoHS Status: Not Compliant

ADE7758
OPERATIONAL MODE REGISTER (0x13)
The general configuration of the ADE7758 is defined by writing to the OPMODE register. Table 18 summarizes the functionality of each
bit in the OPMODE register.
Table 18. OPMODE Register
Bit
Location
0
1
2
3 to 5
6
7
MEASUREMENT MODE REGISTER (0x14)
The configuration of the PERIOD and peak measurements made by the ADE7758 is defined by writing to the MMODE register. Table 19
summarizes the functionality of each bit in the MMODE register.
Table 19. MMODE Register
Bit
Location
0 to 1
2 to 4
5 to 7
Bit
Mnemonic
FREQSEL
PEAKSEL
PKIRQSEL
Bit
Mnemonic
DISHPF
DISLPF
DISCF
DISMOD
SWRST
RESERVED
Default
Value
0
7
7
Default
Value
0
0
1
0
0
0
These bits are used to select the source of the measurement of the voltage line frequency.
FREQSEL1
0
0
1
1
These bits select the phases used for the voltage and current peak registers. Setting Bit 2 switches
the IPEAK and VPEAK registers to hold the absolute values of the largest current and voltage
waveform (over a fixed number of half-line cycles) from Phase A. The number of half-line cycles is
determined by the content of the LINECYC register. At the end of the LINECYC number of half-line
cycles, the content of the registers is replaced with the new peak values. Similarly, setting Bit 3 turns
on the peak detection for Phase B, and Bit 4 for Phase C. Note that if more than one bit is set, the
VPEAK and IPEAK registers can hold values from two different phases, that is, the voltage and
current peak are independently processed (see the Peak Current Detection section).
These bits select the phases used for the peak interrupt detection. Setting Bit 5 switches on the
monitoring of the absolute current and voltage waveform to Phase A. Similarly, setting Bit 6 turns on
the waveform detection for Phase B, and Bit 7 for Phase C. Note that more than one bit can be set for
detection on multiple phases. If the absolute values of the voltage or current waveform samples in
the selected phases exceeds the preset level specified in the VPINTLVL or IPINTLVL registers the
corresponding bit(s) in the STATUS registers are set (see the Peak Current Detection section).
Description
The HPFs in all current channel inputs are disabled when this bit is set.
The LPFs after the watt and VAR multipliers are disabled when this bit is set.
Description
The frequency outputs APCF and VARCF are disabled when this bit is set.
By setting these bits, ADE7758’s ADCs can be turned off. In normal operation, these bits should
be left at Logic 0.
DISMOD[2:0]
0
1
0
1
0
1
0
1
Software Chip Reset. A data transfer to the ADE7758 should not take place for at least 18 μs after
a software reset.
This should be left at 0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Description
Normal operation.
Redirect the voltage inputs to the signal paths for the current channels and
the current inputs to the signal paths for the voltage channels.
Switch off only the current channel ADCs.
Switch off current channel ADCs and redirect the current input signals to the
voltage channel signal paths.
Switch off only the voltage channel ADCs.
Switch off voltage channel ADCs and redirect the voltage input signals to the
current channel signal paths.
Put the ADE7758 in sleep mode.
Put the ADE7758 in power-down mode (reduces AI
Rev. D | Page 64 of 72
FREQSEL0
0
1
0
1
DD
Source
Phase A
Phase B
Phase C
Reserved
to 1 mA typ).