AD9884AKS-140 Analog Devices Inc, AD9884AKS-140 Datasheet - Page 16

• Manufacturer Part Number: AD9884AKS-140
• Description: IC ANALOG INTRFC 140MSPS 128MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9884AKS-140

• Rohs Status: RoHS non-compliant
• Display Type: LCD
• Interface: Analog
• Current - Supply: 135mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Configuration: -
• Digits Or Characters: -

AD9884A
CLOCK GENERATION
A Phase Locked Loop (PLL) is employed to generate the pixel
clock. In this PLL, the HSYNC input provides a reference
frequency. A Voltage Controlled Oscillator (VCO) generates a
much higher pixel clock frequency. This pixel clock is divided
by the value PLLDIV programmed into the AD9884A, and
phase compared with the HSYNC input. Any error is used to shift
the VCO frequency and maintain lock between the two signals.
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,
there is a period during which the signal is slewing from the old
pixel amplitude and settling at its new value. Then there is a
time when the input voltage is stable, before the signal must
slew to a new value (Figure 9). The ratio of the slewing time to
the stable time is a function of the bandwidth of the graphics
DAC and the bandwidth of the transmission system (cable and
termination). It is also a function of the overall pixel rate.
Clearly, if the dynamic characteristics of the system remain
fixed, then the slewing and settling time is likewise fixed. This
time must be subtracted from the total pixel period, leaving the
stable period. At higher pixel frequencies, the total cycle time is
shorter, and the stable pixel time becomes shorter as well.
Any jitter in the pixel clock reduces the precision with which the
sampling time can be determined, and must also be subtracted
from the stable pixel time.
1.0V
0.5V
0.0V
Figure 8. Gain and Offset Control
00h
OFFSET = 0FH
OFFSET = 1FH
OFFSET = 0FH
OFFSET = 1FH
OFFSET = 3FH
OFFSET = 3FH
GAIN
FFh
–16–
Considerable care has been taken in the design of the AD9884A’s
clock generation circuit to minimize jitter. As indicated in Fig-
ure 11 and Table VI, the clock jitter of the AD9884A is less
than 5% of the total pixel time in all operating modes, making
the reduction in the valid sampling time due to jitter negligible.
The PLL characteristics are determined by the loop filter design,
by the PLL Charge Pump Current (CURRENT), and by the
VCO Range setting (VCORNGE). The loop filter design is
illustrated in Figure 10. Recommended settings of VCORNGE
and CURRENT for VESA standard display modes are listed in
Table VII.
Pixel Rate (MHz)
20–60
50–90
80–120
110–140
Pixel Rate
(MSPS)
135
108
94
75
65
50
40
36
25
*AD9884A in oversampled mode.
Table V. Typical K
Table VI. Pixel Clock Jitter vs Frequency
PIXEL CLOCK
Figure 10. PLL Loop Filter Detail
Figure 9. Pixel Sampling Times
0.039 F
3.3k
Jitter p-p
(ps)
350
400
400
450
600
500*
500*
550*
1000*
INVALID SAMPLE TIMES
R
C
Z
Z
VCO
VCORNGE
00
01
10
11
Derived From VCORNGE
C
0.0039 F
P
Jitter p-p
(% of Pixel Time)
4.7%
4.3%
3.4%
3.4%
3.9%
2.4%
2.0%
1.8%
2.5%
PV
FILT
D
K
100
100
150
180
VCO
(MHz/V)
REV. C