MAX6953EAX+T Maxim Integrated Products, MAX6953EAX+T Datasheet - Page 13

• Manufacturer Part Number: MAX6953EAX+T
• Description: IC DRVR DSPL LED 36-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX6953EAX+T

• Display Type: LED
• Configuration: 5 x 7 (Matrix)
• Interface: I²C
• Digits Or Characters: 4 Digits
• Current - Supply: 12mA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Number Of Digits: 4
• Number Of Segments: 140
• Low Level Output Current: 500 mA
• High Level Output Current: 50 mA
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Supply Current: 15 mA
• Maximum Power Dissipation: 941.2 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10. Global Blink Enable/Disable (E Data Bit D3) Format
Table 11. Digit Register Mapping with
Blink Globally Enabled
Table 12. Global Blink Timing Synchronization (T Data Bit D4) Format
Table 13. Global Clear Digit Data (R Data Bit D5) Format
Table 14. Blink Phase Readback (P Data Bit D7) Format
Blink function is disabled.
Blink function is enabled.
Blink timing counters are unaffected.
Blink timing counters are reset during the I
acknowledge.
Digit data for both planes P0 and P1 are unaffected.
Digit data for both planes P0 and P1 are cleared during
I
P1 blink phase
P0 blink phase
2
BIT SETTING
IN PLANE P1
SEGMENT’S
C acknowledge.
0
0
1
1
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
MODE
MODE
______________________________________________________________________________________
BIT SETTING
IN PLANE P0
SEGMENT’S
MODE
MODE
0
1
0
1
Segment off
Segment on only
during the 1st half of
each blink period
Segment on only
during the 2nd half of
each blink period
Segment on
D7
P
P
2
C
BEHAVIOR
SEGMENT
D7
0
1
D6
X
X
D7
P
P
D6
Matrix LED Display Driver
X
X
D7
D6
P
P
X
X
D5
R
R
The E bit globally enables or disables the blink feature
of the device (Table 10). When blink is globally
enabled, then the digit data in both planes P0 and P1
are used to control the display (Table 11).
When blink is globally disabled, then only the digit data
in plane P0 is used to control the display. The digit data
in plane P1 is ignored.
By setting the T bit in multiple MAX6953s at the same
time (or in quick succession), the blink timing can be
synchronized across all the devices (Table 12). Note
that the display multiplexing sequence is also reset,
which might give rise to a one-time display flicker when
the register is written.
Global Blink Timing Synchronization (T Data Bit D4)
Global Blink Enable/Disable (E Data Bit D3) Format
D5
R
R
D6
X
X
D5
R
R
REGISTER DATA
D4
T
T
REGISTER DATA
D4
REGISTER DATA
D5
T
T
0
1
D4
0
1
REGISTER DATA
D3
0
1
D4
T
T
D3
E
E
D3
E
E
D3
E
E
D2
B
B
D2
B
B
D2
B
B
D2
B
B
D1
X
X
D1
D1
X
X
X
X
D1
X
X
Format
D0
D0
D0
S
S
S
S
S
S
D0
S
S
7
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