MAX6963ATH+T Maxim Integrated Products, MAX6963ATH+T Datasheet - Page 15

• Manufacturer Part Number: MAX6963ATH+T
• Description: IC DRIVER LED MATRIX 44-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX6963ATH+T

• Display Type: LED
• Configuration: 8 x 8 (Matrix)
• Interface: 4-Wire Serial
• Digits Or Characters: Any Digit Type
• Current - Supply: 7.5mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFN Exposed Pad
• Number Of Segments: 64
• Low Level Output Current: 750 mA
• High Level Output Current: 48 mA
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Supply Current: 9 mA
• Maximum Power Dissipation: 2162 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

One MAX6960 is designated the master device, and this
is allocated driver address 0. The master’s ADDIN pin is
connected to V+, identifying it as the first device. This
els
ADDOUT pin is connected to the second MAX6960’s
ADDIN pin, and that MAX6960’s ADDOUT pin is connect-
ed to the third MAX6960’s ADDIN, and so on up to 256
MAX6960s. The last MAX6960’s ADDOUT pin is left open
circuit. The last MAX6960 should be the driver for the
bottom-right pixels of the display panel. The ADDOUT
is initialized low at the start of a 3-wire interface configura-
tion operation, and goes high (N + 1.5) ADDCLK periods
later, where n is the driver address of the MAX6960 (0 to
255). See Figures 1 and 2 for connection examples.
The ADDCLK pins for all MAX6960s are all connected
together. ADDCLK data rate is determined by OSC / 4,
nominally 1.048576 MHz. The ADDCLK pin for the master
MAX6960 (driver address 0) is always an output, and all
the other ADDCLKs are always inputs. ADDCLK is active
for exactly 256 clock cycles when a panel configuration is
being performed (on power-up reset, and after a write to
the global panel configuration register).
Table 8. Register Address Map
*
Driver Address (read only)
Pixel Intensity Scale
Panel Intensity
Digit 0 Intensity
Digit 1 Intensity
Fault
—
—
Global Driver Indirect Address*
Global Display Indirect Address LSB*
Global Display Indirect Address
Global Plane Counter*
Global Clear Planes*
Global Panel Configuration*
Global Driver Devices*
Global Driver Rows*
first MAX6960 should be the driver for the top-left pix-
When reading from the global registers, only the master MAX6960 (whose driver address is 0x00) responds.
of
the
REGISTER
3-Wire Interface Clock (ADDCLK)
display
______________________________________________________________________________________
3-Wire Interface Data Lines
(ADDOUT and ADDIN)
panel.
8 x 8 Matrix Graphic LED Drivers
D15
R/W
X
The
master’s
D14
X
X
X
X
X
X
X
X
4-Wire Serially Interfaced
D13
COMMAND ADDRESS
X
X
X
X
X
X
X
X
When the plane counter is configured to automatic mode
(bit 6 of the global plane counter register is set) (Table
30), ADDOUT pulses low for a time of 512/OSC (nominally
122µs) at the start of every automatic plane change. This
signal can be used as an interrupt output from the display
panel to the host to flag that the previous display plane is
now unused and can be written with a new image.
The OSC input for all MAX6960s sharing a 3-wire interface
bus (but not necessarily a 4-wire interface bus) should be
driven by a common CMOS-level clock ranging between
1MHz and 8.5MHz. It is usually necessary to use an exter-
nal clock tree to fan out multiple clock drives when larger
numbers of MAX6960s are used because of the capaci-
tive loads. For example, each one of the eight outputs of a
standard 74HC541 octal buffer could drive 8 to 32
MAX6960 OSC inputs, depending on the layout used.
The recommended setting for OSC is 4.194303MHz. This
frequency sets the slow global plane counter resolution to
1s, and the fast global plane counter resolution to 1Hz.
Use of ADDOUT as Plane Change Interrupt
D12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D11
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D10
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D9
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Multiplex Clock
D8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX CODE
0x0A
0x0B
0x0C
0x0D
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0E
0x0F
(IRQ)
15