AS1120-T austriamicrosystems, AS1120-T Datasheet - Page 8

• Manufacturer Part Number: AS1120-T
• Description: IC DRIVER LCD 46SEGMENTS 64-TQFP
• Manufacturer: austriamicrosystems

Specifications of AS1120-T

• Display Type: LCD
• Configuration: 46 Segment
• Interface: Parallel/Serial
• Current - Supply: 5µA
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -

AS1120
Datasheet - D e t a i l e d D e s c r i p t i o n
The selection of internal or external backplane signal (see Table 5) is initiated after RESETN is disabled – the first ris-
ing edge at pin OSC after RESETN is disabled will force pin BPLOUT to deliver the internally generated backplane sig-
nal. If there is no rising edge at pin OSC, BPLOUT will simply buffer the signal at pin BPLIN.
Table 5. Backplane Source Generation Selection
Note: The LCD should never be supplied with static signals. Verify that signals at pins BPLIN and BPLOUT are
Internal Mode – R/C Oscillator Running (Generating the Backplane)
Connect external R/C components to pin OSC as shown in Figure 1 on page 1. When an external R
connected to pin OSC, a clock signal whose frequency is equal to f
Note: Internal mode requires that pin BPLIN be connected to pin BPLOUT.
The oscillation period is approximately t
quency and the generated frequency increases as indicated in Table 6.
Table 6. Oscillator Error Rate
Figure 7. AS1120 Clock Circuit
External Mode: R/C Oscillator Stopped (External Backplane)
Connect pin OSC to V
should be presented at pin BPLIN, which will be regenerated and presented at pin BPLOUT.
www.austriamicrosystems.com/LCD-Driver-ICs/AS1120
always running while V
External
Internal
Mode
RESETN
BPLIN
OSC
Expected Oscillator Frequency
V
43
DD
15
13
11
SS
in order to block the internal oscillator. In this external mode, an external backplane signal
DD
100 kHz
10 kHz
50 kHz
1 kHz
is supplied; note that pin BPLOUT is stopped during a reset.
Oscillator
D
CLRN
OSC
Q
= 1/f
OSC Pin
Tied Low
Running
OSC
= 0.69 x R
f
Revision 1.06
OSC
CLRN
/16
EXT
OSC
x C
EXT
divided by 16 will be present at pin BPLOUT.
SEL
A
B
, and the error between the expected fre-
AS1120
BPLOUT
f
BPLIN
OSC
Error
40%
12
BPLOUT
20%
1%
5%
/16
EXT
and C
EXT
8 - 13
are