ISL6884IAZ Intersil, ISL6884IAZ Datasheet - Page 7

IC CTRLR CCFL BRIGHTNESS 20-SSOP

ISL6884IAZ

Manufacturer Part Number
ISL6884IAZ
Description
IC CTRLR CCFL BRIGHTNESS 20-SSOP
Manufacturer
Intersil
Datasheet

Specifications of ISL6884IAZ

Display Type
CCFL - Cold Cathode Fluorescent Lamp
Interface
I²C
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Configuration
-
Digits Or Characters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL6884IAZ
Manufacturer:
Intersil
Quantity:
480
ISL6884
2
I
C Register Description
Register addresses and default values are given in the
following Register Description Table.
2
I
C Slave Address - ISL6884’s slave address is:
• 1101_1111 for reading
• 1101_1110 for writing
BRT_M - Master Brightness Control input. This register
controls the duty cycle of al 8 DPWM outputs.
BRT_OS[1..8] - Brightness offset. These registers allow the
system designer to increase or decrease the duty cycle of
individual channel to equalize the brightness of all lamps in a
system. Note: Value is stored as 2’s complement number.
MSTR_EN - Master Enable, This signal is AND’ed with the
EN pin to create the enable for the PWM dimming output. If
this bit OR the EN pin is low the DPWM outputs are held low.
CH_EN - Individual Channel Enables for each DPWM
output. If only DPWM 1, 3, 5 and 7 are to be used, CH_EN
bits 1, 3, 5, and 7 should be set to 1 and bits 2, 4, 6, and 8
should be set to 0.
FLT_TOUT - Fault Timer Time Out Setting. This register
controls the response of the ISL6884 to a logic low input on
the LAMPON pin (indicating that one or more lamps is NOT
ON). A value between 0X01 and 0XFF in the FLT_TOUT
register will set the time that ISL6884 will operate with a low
signal at the LAMPON pin (fault time out). The adjustment
range is from less than 0.1 second to approximately 2
seconds. The power on reset default time out is 1 second.
After a fault time out, all DPWM outputs are latched low until
power is cycled. If FLT_TOUT is set to 0X00, ISL6884 will
not time out and will continue to operate even with a low
signal at the LAMPON pin.
STATUS - indicates the status of the Time out Fault,
LAMPON input signal and ENABLE (MSTR_EN AND EN
pin).
7
FN9265.0
March 9, 2006

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