AY0438-I/P Microchip Technology, AY0438-I/P Datasheet - Page 2

• Manufacturer Part Number: AY0438-I/P
• Description: IC LCD DRIVER CMOS 32SEG 40DIP
• Manufacturer: Microchip Technology

Specifications of AY0438-I/P

• Package / Case: 40-DIP (0.600", 15.24mm)
• Display Type: LCD
• Configuration: 32 Segment
• Interface: Parallel
• Digits Or Characters: 16 Characters
• Current - Supply: 25µA
• Voltage - Supply: 3 V ~ 8.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Number Of Digits: 4
• Number Of Segments: 32
• Maximum Clock Frequency: 1.5 MHz
• Operating Supply Voltage: 3 V to 8.5 V
• Maximum Power Dissipation: 250 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 60 uA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AY0438
FIGURE 1: PIN DESCRIPTIONS
FIGURE 2: BLOCK DIAGRAM
FIGURE 4: TIMING DIAGRAM
1.0
1.1
The shift register shifts and outputs on the falling edge
of the clock. Every clock falling edge does a logical left
shift. As an example, if 32 clock pulses are supplied as
in Figure 4, then the data input at the first clock will out-
put at SEG 32, and the last data input (# 32) will output
at SEG 1 when a LOAD signal is enabled (Figure 2). It
is recommended that a complete 32 bit transfer be
done every time the outputs are updated. A logic 1 at
the Data In causes the corresponding segment to be
DS70010I-page 2
LCD
Data out
CLOCK
Data in
Load
3-29, 32, 33, 37-39
Pin # (PDIP Only)
Data in
Load
OPERATION:
Data In and Clock
Clock
Generator
LCD AC
30
31
34
35
36
40
1
2
32-bit Static Shift Register
32 Segment Drivers
START
32 Latches
1
Seg 1-32
Data Out
Data In
Name
LCD
Clock
Load
V
V
SEG 32
BP
DD
SS
Data out
32 Outputs
Backplane
output
Direction
Ground
Output
Output
Output
Input
Input
Input
Input
-
FIGURE 3: BACKPLANE AND SEGMENT
enabled or visible, i.e. the output at Segment Output is
180
(Figure 3).
1.2
A logic 1 at the Load input (Figure 2) causes the paral-
lel load of the data in the shift register into the latches
that control the segment drivers. If the Load signal is
tied high, then the latches become transparent and the
segment drivers are always connected to the shift reg-
isters.
out-of-phase
31
Load
Backplane
1/f
SEG On
SEG Off
SEG 2
Data output from shift register
OUTPUT
Data input to shift register
Latch data from registers
Backplane drive output
Backplane drive input
Direct drive outputs
System clock input
Supply voltage
Description
with
Ground
32
t
1995 Microchip Technology Inc.
DS
the
SEG 1
t
PD
t
DH
Backplane
t
PW
output