CP2400-GM Silicon Laboratories Inc, CP2400-GM Datasheet - Page 54

• Manufacturer Part Number: CP2400-GM
• Description: IC LCD DRIVER 48QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2400-GM

• Package / Case: 48-QFN
• Display Type: LCD
• Configuration: 128 Segment
• Interface: SPI Serial
• Current - Supply: 620µA
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1855-5

CP2400/1/2/3
SFR Definition 9.1. ULPCN: Ultra Low Power Control Register
Address = 0xA2
Note: The state of ULPPMPOL should not be changed in the same write which enables the ULP modes. Rather, the state of
54
Name
Reset
7:5
Bit
Type
4
3
2
1
0
Bit
ULPPMPOL Ultra Low Power Port Match Polarity.
ULPPMPOL should be set first, then the ULP mode should be enabled.
Reserved
RTCDIS
Unused
LCDEN
ULPEN
Name
R/W
7
0
Read = 000b. Write = Don’t Care.
Ultra Low Power Mode SmaRTClock Disable.
When set to 1, the SmaRTClock oscillator will be disabled two SmaRTClock cycles after entry
into ULP Mode. This allows the device to enter its Shutdown Mode.
Any write operation that sets this bit to 1b must also set ULPEN to 1b.
Ultra Low Power LCD Enable.
When set to 1, LCD Functionality is enabled in ULP mode. Rising edge transitions on NSS
and PWR disable the internal LDO and place the device into the ultra low power mode. A
falling edge transition on NSS or PWR will re-enable the regulator and return the device to
normal power mode. This bit is self-clearing upon wake-up from the ultra low power mode.
Read = 0b. Must write 0b.
Ultra Low Power Port Match Enable.
When set to 1, Port Match Functionality is enabled in ULP mode. Rising edge transitions on
NSS and PWR disable the internal LDO and place the device into the ultra low power mode. A
falling edge transition on NSS or PWR will re-enable the regulator and return the device to
normal power mode. This bit is self-clearing upon wake-up from the ultra low power mode.
0: ULP Port Match wake-up occurs on rising edge transitions (level sensitive).
1: ULP Port Match wake-up occurs on falling edge transitions (level sensitive).
R/W
6
0
R/W
5
0
RTCDIS
Rev. 1.0
R/W
4
0
LCDEN
Function
R/W
3
0
Reserved
R/W
2
0
ULPEN
R/W
1
0
ULPPMPOL
R/W
0
0