X3100V28T1 Intersil, X3100V28T1 Datasheet

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... OVT UVT OCT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. X3100, X3101 4 Cell/3 Cell FN8110.1 OVP/LMON AS0 ...

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... NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ...

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Pin Descriptions (Continued) PIN NUMBER PIN NAME 4 CB2 Cell balancing FET control output 2. These outputs are used to switch an external FETs in order to perform cell voltage balancing control. This function can be used to adjust individual ...

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Pin Descriptions (Continued) PIN NUMBER PIN NAME 23 OVP/ Over-charge Voltage Protection output/Load Monitor output. This one pin performs two functions depending upon the LMON present mode of operation of the X3100 or X3101. Over-charge Voltage Protection (OVP) This pin ...

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Power to the X3100 or X3101 is applied to pin VCC via diodes D6 and D7. These diodes allow the device to be powered by the Li-Ion battery cells in normal operating conditions, and allow the device to be powered ...

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Monitor Function” on page 21). FETs Q4 and Q5 may be required on general purpose I/Os of the microcontroller that connect outside of the package. In some cases, without FETs, pull-up resistors external to the pack ...

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Typical Application Circuit 7 X3100, X3101 FN8110.1 January 3, 2008 ...

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Power-up Timing (Initial Power-up or after Sleep Mode) V SLR VCC 0V V RGO 0V VOLTAGE REGULATOR OUTPUT STATUS (INTERNAL SIGNAL) VRGS OVERCURRENT DETECTION STATUS (INTERNAL SIGNAL) OCDS STATUS REGISTER BIT 0 VRGS+OCDS STATUS REGISTER BIT 2 (SWCEN = 0) ...

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Configuration Register The X3100 and X3101 can be configured for specific user requirements using the Configuration Register. TABLE 1. CONFIGURATION REGISTER FUNCTIONALITY BIT(s) NAME – (don’t care) 6 SWCEN Switch Cell Charge Enable threshold function ON/OFF 7 ...

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Cell Number Selection The X3100 is designed to operate with four (4) Li-Ion battery cells. The X3101 is designed to operate with three (3) Li-ion battery cells. The CELLN bit of the configuration register (Table 9) sets the number of ...

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Figure 2. Writing to Configuration Register Power-up Data Recalled from Shadow EEPROM to SRAM Configuration Register (SRAM = Old Value) WCFIG (New Value) Configuration Register (Sram = New Value) Store (New Value Shadow EEPROM Power-down- power-on Data Recalled ...

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Current Sense Gain (CSG1, CSG0) These bits set the gain of the current sense amplifier. These are x10, x25, x80 and x160. For more detail, see section “Current Monitor Function” on page 21. Table 14. Current Sense Gain Control Control ...

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Bit 1 of the status register simply indicates whether or not the X3100 or X3101 is in over-discharge protec- tion mode. Bit 2 of the status register (CCES+OVDS) indicates the status of two conditions of the X3100 or X3101. Cell ...

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Over-charge Protection The X3100 and X3101 monitor the voltage on each battery cell ( for any cell, V CELL time exceeding T , then the Charge FET will be OV switched OFF (OVP/LMON = V CC now entered ...

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Table 20. Over-charge Protection Mode—Event Diagram Description Event [0,1) — Discharge FET is ON (UVP/OCP = V — Charge FET is ON (OVP/LMON = V — All cell voltages (V CELL — The device is in normal operation mode (i.e. ...

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Over-discharge Protection If V < for a time exceeding T CELL UV said over-discharge state (Figure 4). In this instance, the X3100 and X3101 automatically switch the discharge FET OFF (UVP/OCP = Vcc), and ...

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Figure 4. Over-discharge Protection Mode—Event Diagram VCC VCELL V UV UVP/OCP OVP/LMON RGO Event 1 0 Note 1: If SWEN = 0 and V < then OVP/LMON stays high and charging is prohibited. CELL CE Note 2: OVP/LMON ...

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Table 22. Over-discharge Protection Mode—Event Diagram Description Event [3] Return from sleep mode (but still in over-discharge protection mode): — Vcc rises above the “Return from Sleep mode threshold Voltage” (V case that the battery pack was connected to a ...

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Over-Current Protection In addition to monitoring the battery cell voltages, the X3100 and X3101 continually monitor the voltage VCS (VCS - VCS ) across the current sense resis tor ( VCS > V for a ...

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Figure 6. Over-Current Protection Mode—Event Diagram Normal Operation Mode VCS UVP/OCP Event 0 1 Table 24. Over-Current Protection Mode—Event Diagram Description Event [0,1) — Discharge FET is ON (OCP = Vss). Battery cells ...

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Table 24. Over-Current Protection Mode—Event Diagram Description Event [3] — The device detects the load resistance has risen above R — Voltages P+ and VCS — The test current from pin OVP/LMON is stopped (I — The device has now ...

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The internal gain of the X3100 or X3101 current sense voltage amplifier can be selected by using the WCNTR Instruction to set bits CSG1 and CSG0 in the control register (Table 14). The CSG1 and CSG0 bits select one of ...

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... IDLock Memory Intersil’s IDLock memory provides a flexible mecha- nism to store and lock battery cell/pack information. There are seven distinct IDLock memory areas within the array which vary in size from one page to as much as half of the entire array ...

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Table 30. X3100/X3101 Instruction Set Instruction Instruction Name Format* WREN 0000 0110 WRDI 0000 0100 EEWRITE 0000 0010 EEREAD STAT 0000 0101 EEREAD 0000 0011 WCFIG 0000 1001 WCNTR 0000 1010 RDSTAT 0000 1011 SET IDL 0000 0001 *Instructions have ...

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EEPROM Write Sequence (EEWRITE) Prior to any attempt to write data into the EEPROM of the X3100 or X3101, the “Write Enable” latch must first be set by issuing the WREN instruction (See Table 30 and Figure 9 ...

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Figure 11. EEPROM Page Write (EEWRITE) Operation Sequence SCK EEWRITE Instruction SCK Data Byte Figure 12. EEPROM ...

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EEPROM Read Sequence (EEREAD) When reading from the X3100 or X3101 EEPROM memory first pulled LOW to select the device. The 8-bit EEREAD instruction is transmitted to the X3100 or X3101, followed by the 16-bit address, of which ...

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Write Configuration Register (WCFIG) The Write Configuration Register (WCFIG) instruc- tion updates the static part of the Configuration Reg- ister. These new values take effect immediately, for example writing a new Over-discharge voltage limit. However, to make these changes permanent, ...

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Read Status Register (RDSTAT) The Read Status Register (RDSTAT) command returns the status of the X3100 or X3101. The Status Register contains three bits that indicate whether the voltage regulator is stabilized, and if there are any pro- tection failure ...

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ABSOLUTE MAXIMUM RATINGS Symbol Storage temperature Operating temperature DC output current Lead temperature (soldering 10 seconds) VCC Power supply voltage VCELL Cell voltage V Terminal voltage (Pins: SCK, SI, SO, CS, AS0, AS1, AS2, VCS1, TERM1 VCS2, OVT, UVT, OCT, ...

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OPERATING CHARACTERISTICS X3100 (Over the recommended operating conditions unless otherwise specified) Description 5V regulated voltage 5VDC voltage regulator current limit V supply current ( supply current ( supply current ( supply current (4) CC ...

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Description Over-current mode detection voltage (Default in Boldface) Over-current mode detection time Over-current mode release time Load resistance over-current mode release condition Cell charge threshold voltage X3100 wake-up voltage (For Vcc above this voltage, the device wakes up) X3100 sleep ...

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OPERATING CHARACTERISTICS X3101 (Over the recommended operating conditions unless otherwise specified) Description 5V regulated voltage 5VDC voltage regulator current limit V supply current ( supply current ( supply current ( supply current (4) CC ...

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Description Over-current mode detection voltage (Default in Boldface) Over-current mode detection time Over-current mode release time Load resistance over-current mode release condition Cell charge threshold voltage X3101 wake-up voltage (For Vcc above this voltage, the device wakes up) X3101 sleep ...

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POWER-UP TIMING Symbol (6) t Power-up to SPI read operation (RDSTAT, EEREAD STAT) PUR (6) t Power-up to SPI write operation (WREN, WRDI, EEWRITE, WCFIG, SET IDL, WCNTR) PUW1 (6) t Power-up to SPI write operation (WCNTR - bits 10 ...

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A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) SERIAL INPUT TIMING Symbol Parameter f Clock frequency SCK t Cycle time CYC t CS lead time LEAD t CS lag time LAG t Clock HIGH time WH t Clock ...

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Serial Output Timing Symbol Parameter f Clock Frequency SCK t Output Disable Time DIS t Output Valid from Clock LOW V t Output Hold Time HO (11) t Output Rise Time RO (11) t Output Fall Time FO Notes: (11)This ...

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Analog Output Response Time Symbol t AO Output Stabilization Time (Voltage Source Change) VSC t AO Output Stabilization Time (Current Sense Gain Change) CSGO t Control Outputs Response Time (UVP/OCP, OVP/MON, CB4, CO CB3, CB2, CB1, RGC) ANALOG OUTPUT RESPONSE ...

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TYPICAL OPERATING CHARACTERISTICS Norm al Operating Current 150 125 100 75 50 -20 25 Tem perature X3100/X3101 Over Charge Trip Voltage (Typical) 4.40 4.35 4.30 4.25 4.20 4.15 -25 25 Temperature (Deg C) 4.2V Setting 4.3V Setting X3101 Over Discharge ...

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X3100, X3101 40 FN8110.1 January 3, 2008 ...

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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...